METHOD OF CONTACT FORMATION BETWEEN METAL AND SEMICONDUCTOR

• US 20180076324A1
• Filed: 01/24/2017
• Published: 03/15/2018
• Est. Priority Date: 09/14/2016
• Status: Abandoned Application

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: HUANG, Yi-Chiau, CHUNG, Hua, LI, Xuebin
• Application Number:
  US15/414,080
• Publication Number:
  US 20180076324A1
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/28512 on semiconductor bodies comprising elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 21/28525 the conductive layers comprising semiconducting material H01L21/28518, H01L21/28537 take precedence
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/41783 Raised source or drain electrodes self aligned with the gate
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66643 with source or drain regions formed by a Schottky barrier or a conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/7839 with Schottky drain or source contact

Abstract

Implementations of the present disclosure generally relate to improved semiconductor devices and methods of manufacture thereof. More specifically, implementations disclosed herein relate to a semiconductor device having an improved contact interface between the semiconductor material and metal material and methods of manufacture thereof. The method includes forming a semiconductor layer on a silicon substrate, forming an interfacial layer over the semiconductor layer, and forming a metal contact layer over the interfacial layer. The interfacial layer comprises one or more of germanium, boron, gallium, indium, thallium, arsenic, antimony, tin, silicon, and phosphorus, and has a thickness of between about 50 angstroms and about 100 angstroms. The interfacial layer improves the quality of the contact interface between the semiconductor material and metal material.

Claims

1. A method for forming a device, comprising:

forming a semiconductor layer on a silicon substrate;

forming an interfacial layer over the semiconductor layer, wherein the interfacial layer comprises one or more of germanium, boron, gallium, indium, thallium, arsenic, antimony, tin, silicon, and phosphorus, and wherein the interfacial layer has a thickness of between about 50 angstroms and about 100 angstroms; and

forming a metal contact layer over the interfacial layer.

2. The method for forming a device of claim 1, wherein the semiconductor layer is separated by a channel layer.

3. The method for forming a device of claim 2, wherein an insulating layer is deposited on the channel layer.

4. The method for forming a device of claim 3, wherein a gate layer is deposited on the insulating layer.

5. The method for forming a device of claim 1, wherein at least one probe is connected to the metal contact layer.

6. The method for forming a device of claim 4, wherein at least two probes are connected to the metal contact layer.

7. A device, comprising:

a silicon substrate;

a semiconductor layer contacting the silicon substrate;

an interfacial layer contacting the semiconductor layer, wherein the interfacial layer comprises one or more of germanium, boron, gallium, indium, thallium, arsenic, antimony, tin, silicon, and phosphorus, and wherein the interfacial layer has a thickness of between about 50 angstroms and about 100 angstroms; and

a metal contact layer contacting the interfacial layer.

8. The device of claim 7, wherein the semiconductor layer is separated by a channel layer.

9. The device of claim 8, wherein an insulating layer contacts the channel layer.

10. The device of claim 9, wherein a gate layer contacts the insulating layer.

11. The device of claim 7, wherein at least one probe is connected to the metal contact layer.

12. The device of claim 10, wherein at least two probes are connected to the metal contact layer.

13. The device of claim 7, wherein the semiconductor layer comprises SiGe or SiGeB and the interfacial layer comprises GeB.

14. A device, comprising:

a silicon substrate;

a first semiconductor layer and a second semiconductor layer contacting the silicon substrate, wherein the first semiconductor layer and the second semiconductor layer are separated by a channel layer, an insulating layer contacts the channel layer, and a gate layer contacts the insulating layer;

a first interfacial layer contacting the first semiconductor layer and a second interfacial layer contacting the second semiconductor layer, wherein the first interfacial layer and the second interfacial layer comprise one or more of germanium, boron, gallium, indium, thallium, arsenic, antimony, tin, silicon, and phosphorus, and wherein the first interfacial layer and the second interfacial layer have a thickness of between about 50 angstroms and about 100 angstroms; and

a first metal contact layer contacts the first interfacial layer and a second metal contact layer contacts the second interfacial layer.

15. The device of claim 14, further comprising a first probe connected to the first metal contact layer and a second probe connected to the second metal contact layer, wherein the first metal contact layer and the second metal contact layer comprise titanium.

16. The device of claim 14, wherein the first interfacial layer and the second interfacial layer have a thickness of between about 50 angstroms and about 100 angstroms.

17. The device of claim 14, wherein the first semiconductor layer and the second semiconductor layer comprise SiGe or SiGeB.

18. The device of claim 17, wherein the first interfacial layer and the second interfacial layer comprise GeB.

19. The device of claim 17, wherein the first interfacial layer and the second interfacial layer comprise GeSn.

20. The device of claim 14, wherein the first metal contact layer and the second metal contact layer comprise tantalum.