DISPLAY PANEL, DISPLAY DEVICE AND METHOD FOR MAKING THE SAME

• US 20180077371A1
• Filed: 06/29/2016
• Published: 03/15/2018
• Est. Priority Date: 03/04/2016
• Status: Active Grant

• Current Assignee: BOE Technology Group Co., Ltd.
• Original Assignee: BOE Technology Group Co., Ltd.
• Inventors: Park, Hanjun
• Granted Patent: US 10,136,089 B2
• Time in Patent Office: Days
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2300/0469 Details of the physics of pixel operation
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2360/141 the light conveying information used for selecting or modulating the light emitting or modulating element
• CPC Class Codes: G09G 3/30 using electroluminescent panels
• CPC Class Codes: G09G 3/3225 using an active matrix
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1262 with a particular formation, treatment or coating of the substrate
• CPC Class Codes: H01L 31/153 formed in, or on, a common substrate
• CPC Class Codes: H04N 25/702 SSIS architectures characterised by non-identical, non-equidistant or non-planar pixel layout
• CPC Class Codes: H04N 25/745 Circuitry for generating timing or clock signals
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors
• CPC Class Codes: H04N 25/77 Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
• CPC Class Codes: H10K 59/65 OLEDs integrated with inorganic image sensors

Abstract

A display panel, a display device including the same and a method for making the display panel are disclosed in the embodiments of the disclosure. The display panel includes: a drive module and a plurality of pixel units. Each pixel unit of the plurality of pixel units has a plurality of sub-pixel units and a plurality of image sensing units, each of the plurality of sub-pixel units being corresponding to each of the plurality of image sensing units respectively; each sub-pixel unit of the plurality of pixel units and each image sensing unit of the plurality of image sensing units are connected to the drive module, each sub-pixel unit being arranged to be adjacent to an image sensing unit corresponding thereto; and the drive module is configured to drive the plurality of image sensing units so as to take images, and to drive the plurality of sub-pixel units as so to display the images.

Claims

1. A display panel, comprising:

a drive module; and

a plurality of pixel units,

wherein each pixel unit of the plurality of pixel units has a plurality of sub-pixel units and a plurality of image sensing units, each of the plurality of sub-pixel units corresponding to each of the plurality of image sensing units respectively;

wherein each sub-pixel unit of the plurality of pixel units and each image sensing unit of the plurality of image sensing units are connected to the drive module, each sub-pixel unit being arranged to be adjacent to an image sensing unit corresponding thereto; and

wherein the drive module is configured to drive the plurality of image sensing units so as to take images, and to drive the plurality of sub-pixel units so as to display the images.

2. The display panel according to claim 1, wherein the display panel further comprises a plurality of gate lines, a plurality of data lines and a plurality of read-out lines;

wherein each image sensing unit is connected to two adjacent gate lines and to one adjacent read-out line; and

wherein each sub-pixel unit is connected to one of the two adjacent gate lines and to one adjacent data line.

3. The display panel according to claim 2, wherein each image sensing unit comprises a first transistor, a second transistor and an image sensing layer;

wherein a gate of the first transistor is connected to the one of the two adjacent gate lines, a first electrode of the first transistor is connected to the image sensing layer and a second electrode of the first transistor is connected to a common electrode of the display panel; and

wherein a first electrode of the second transistor is connected to the image sensing layer, a second electrode of the second transistor is connected to the one read-out line and a gate of the second transistor is connected to the other one of the two adjacent gate lines.

4. The display panel according to claim 3, wherein the image sensing layer comprises a first electrode layer, a quantum film layer and a second electrode layer, and wherein:

the quantum film layer is located between the first electrode layer and the second electrode layer,

the first electrode layer is connected with the first electrode of the first transistor and the first electrode of the second transistor respectively, and

the first electrode layer and the second electrode layer are connected with both ends of a power supply respectively.

5. The display panel according to claim 2, wherein each sub-pixel unit comprises a third transistor and a display layer, and

wherein a gate of the third transistor is connected to the one of the two adjacent gate lines, a first electrode of the third transistor is connected to the one adjacent data line, and a second electrode of the third transistor is connected to the display layer.

6. The display panel according to claim 5, wherein the display layer comprises a third electrode layer, a light-emitting layer, and a fourth electrode layer, and wherein:

the light-emitting layer is located between the third electrode layer and the fourth electrode layer,

the third electrode layer is connected to the second electrode of the third transistor; and

the third electrode layer and fourth electrode layer are connected with both ends of the power supply respectively.

7. The display panel according to claim 2, wherein the drive module comprises a timing controller, a gate line integrated circuit, a data line integrated circuit and an image sensing read-out line integrated circuit;

wherein the timing controller is electrically connected with the gate line integrated circuit, the data line integrated circuit, the image sensing read-out line integrated circuit, and

wherein the gate line integrated circuit is electrically connected with the plurality of gate lines, the data line integrated circuit is electrically connected with the plurality of data lines and the image sensing read-out integrated circuit is electrically connected with the plurality of read-out lines.

8. A display device, comprising the display panel according to claim 1.

9. A method for making a display panel, comprising steps of:

forming a plurality of sub-pixel units and a plurality of image sensing units within an area corresponding to each pixel unit on a substrate, the plurality of sub-pixel units being corresponding to the plurality of the image sensing units respectively, and each sub-pixel unit being arranged to adjacent to its corresponding image sensing unit; and

connecting each of the plurality of the sub-pixel units with a drive module, and

connecting each of the plurality of image sensing units with the drive module.

10. The method according to claim 9, wherein the step of forming the plurality of sub-pixel units and the plurality of image sensing units within the area corresponding to each pixel unit on the substrate comprises:

forming a first transistor, a second transistor and a third transistor within the area corresponding to each pixel unit on the substrate;

forming a passivation layer on the first transistor, the second transistor and the third transistor; and

forming an image sensing layer and a display layer on the passivation layer, and connecting the image sensing layer with the first transistor and the second transistor respectively and connecting the display layer with the third transistor.

11. The method according to claim 9, wherein the step of forming the plurality of sub-pixel units and the plurality of image sensing units within the area corresponding to each pixel unit on the substrate comprises:

forming a plurality of gate lines, a plurality of data lines and a plurality of read-out lines simultaneously when forming the first transistor, the second transistor and the third transistor.

12. The method according to claim 10, wherein the step of forming the image sensing layer and the display layer on the passivation layer comprises:

forming a first electrode layer and a third electrode layer on the passivation layer, and connecting the first electrode layer with the first transistor and the second transistor respectively, and connecting the third electrode layer with the third transistor;

forming a quantum film layer on the first electrode layer;

forming a light-emitting layer on the third electrode layer; and

forming a second electrode layer on the quantum film layer and forming a fourth electrode layer on the light-emitting layer.

13. The method according to claim 10, wherein the image sensing layer is formed by a mask exposure process.