MEMORY VIOLATION PREDICTION
First Claim
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1. A method for preventing memory violations, comprising:
- accessing, by a fetch unit from a branch predictor of a processor, a disambiguation indicator associated with a block of instructions of a program to be executed by the processor;
fetching, by the fetch unit of the processor from an instruction cache, the block of instructions; and
executing, by the processor, load instructions and/or store instructions in the block of instructions based on the disambiguation indicator indicating whether or not the load instructions and/or the store instructions in the block of instructions can bypass other instructions of the program or be bypassed by other instructions of the program.
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Abstract
Disclosed are methods and apparatuses for preventing memory violations. In an aspect, a fetch unit accesses, from a branch predictor of a processor, a disambiguation indicator associated with a block of instructions of a program to be executed by the processor, and fetches, from an instruction cache, the block of instructions. The processor executes load instructions and/or store instructions in the block of instructions based on the disambiguation indicator indicating whether or not the load instructions and/or the store instructions in the block of instructions can bypass other instructions of the program or be bypassed by other instructions of the program.
40 Citations
30 Claims
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1. A method for preventing memory violations, comprising:
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accessing, by a fetch unit from a branch predictor of a processor, a disambiguation indicator associated with a block of instructions of a program to be executed by the processor; fetching, by the fetch unit of the processor from an instruction cache, the block of instructions; and executing, by the processor, load instructions and/or store instructions in the block of instructions based on the disambiguation indicator indicating whether or not the load instructions and/or the store instructions in the block of instructions can bypass other instructions of the program or be bypassed by other instructions of the program. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 30)
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14. An apparatus for preventing memory violations, comprising:
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a processor; a fetch unit configured to fetch, from an instruction cache, a block of instructions of a program to be executed by the processor; and a branch predictor configured to provide a disambiguation indicator associated with the block of instructions to the processor, wherein the processor is configured to execute load instructions and/or store instructions in the block of instructions based on the disambiguation indicator indicating whether or not the load instructions and/or the store instructions in the block of instructions can bypass other instructions of the program or be bypassed by other instructions of the program. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26)
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27. An apparatus for preventing memory violations, comprising:
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a means for processing; a means for fetching configured to fetch, from an instruction cache, a block of instructions of a program to be executed by the processor; and a means for branch prediction configured to provide a disambiguation indicator associated with the block of instructions to the processor, wherein the means for processing is configured to execute load instructions and/or store instructions in the block of instructions based on the disambiguation indicator indicating whether or not the load instructions and/or the store instructions in the block of instructions can bypass other instructions of the program or be bypassed by other instructions of the program. - View Dependent Claims (28)
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29. A non-transitory computer-readable medium storing computer-executable code for preventing memory violations, the computer-executable code comprising:
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at least one instruction to cause a fetch unit of a processor to fetch, from an instruction cache, a block of instructions of a program to be executed by the processor; at least one instruction to cause the fetch unit to access, from a branch predictor of the processor, a disambiguation indicator associated with the block of instructions; and at least one instruction to cause the processor to execute load instructions and/or store instructions in the block of instructions based on the disambiguation indicator indicating whether or not the load instructions and/or the store instructions in the block of instructions can bypass other instructions of the program or be bypassed by other instructions of the program.
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Specification