NON-VOLATILE MEMORY WITH READ MODES

• US 20180089024A1
• Filed: 09/23/2016
• Published: 03/29/2018
• Est. Priority Date: 09/23/2016
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Hahn, Judah Gamliel, Vishne, Gadi, Lehmann, Joshua, Bazarsky, Alexander, Navon, Ariel
• Granted Patent: US 10,223,199 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 16/32 Timing circuits
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: H04L 1/0015 characterised by the adaptation strategy
• CPC Class Codes: H04L 1/0017 where the mode-switching is based on Quality of Service requirement
• CPC Class Codes: H04L 1/0025 Transmission of mode-switching indication
• CPC Class Codes: H04L 1/0026 Transmission of channel quality indication
• CPC Class Codes: H04L 1/004 by using forward error control H04L1/0618 takes precedence; coding, decoding or code conversion, for error detection or correction H03M13/00
• CPC Class Codes: H04L 41/5022 : by giving priorities, e.g. assigning classes of service
• CPC Class Codes: H04L 41/5025 : by proactively reacting to service quality change, e.g. by reconfiguration after service quality degradation or upgrade
• CPC Class Codes: H04L 65/80 : Responding to QoS

Abstract

A non-volatile memory system receives a request to read data. That request includes a quality of service indication. The memory system performs a read process that satisfies the quality of service indication and identifies a set of data with errors. The memory system returns the set of data with errors in response to the request.

Claims

1. A non-volatile storage apparatus, comprising:

a plurality of non-volatile memory cells; and

one or more control circuits in communication with the memory cells, the one or more control circuits are configured to receive a request to read that includes a quality of service indication and perform a read process for the memory cells that identifies a set of data with errors, the read process satisfies the quality of service indication, the one or more control circuits are configured to return the set of data with errors in response to the request to read.

2. The non-volatile storage apparatus of claim 1, wherein:

the quality of service indication indicates a number of errors; and

the returned set of data includes a number of errors that is less than the number of errors.

3. The non-volatile storage apparatus of claim 1, wherein:

the quality of service indication indicates a timing constraint for responding to the request to read; and

the one or more control circuits are configured to perform the read process within the timing constraint.

4. The non-volatile storage apparatus of claim 1, wherein:

the quality of service indication indicates a power limitation for responding to the request to read; and

the one or more control circuits are configured to perform the read process within the power limitation.

5. The non-volatile storage apparatus of claim 1, wherein:

the one or more control circuits are configured to choose a read mode based on the quality of service indication; and

the one or more control circuits are configured to perform the read process according to the chosen read mode.

6. The non-volatile storage apparatus of claim 1, wherein:

the one or more control circuits are configured to identify one or more portions of the returned set of data that include the errors.

7. The non-volatile storage apparatus of claim 1, wherein:

the one or more control circuits are configured to decode code words read from the memory cells as part of the read process; and

the one or more control circuits are configured to return the set of data with errors in response to the request to read because the one or more control circuits are unable to completely decode all of the code words read from the memory cells.

8. The non-volatile storage apparatus of claim 1, wherein:

the quality of service indication indicates a maximum number of errors;

the one or more control circuits are configured to correct errors in information sensed from the memory cells; and

the one or more control circuits are configured to stop the read process when a number of uncorrected errors in the information sensed from the memory cells satisfies the maximum number of errors.

9. The non-volatile storage apparatus of claim 1, wherein:

the quality of service indication indicates a maximum number of errors;

the one or more control circuits are configured to correct errors in information sensed from the memory cells; and

the one or more control circuits are configured to stop the read process when all correctable errors in the information sensed from the memory cells have been corrected and then test whether an amount of remaining errors satisfies the maximum number of errors.

10. The non-volatile storage apparatus of claim 1, wherein:

the one or more control circuits are configured to receive a request to program that includes a quality indication; and

the one or more control circuits are configured to perform programming of the memory cells based on the received quality indication.

11. The non-volatile storage apparatus of claim 10, wherein:

the one or more control circuits are configured to choose a code rate based on the received quality indication; and

the one or more control circuits are configured to perform the programming including implementing an error correction encoding process using the chosen code rate.

12. The non-volatile storage apparatus of claim 10, wherein:

the one or more control circuits are configured to choose a number of bits per memory cell based on the received quality indication; and

the one or more control circuits are configured to perform the programming into the memory cells at the chosen number of bits per memory cell.

13. The non-volatile storage apparatus of claim 10, wherein:

the one or more control circuits are configured to choose a threshold voltage window size for the programming based on the received quality indication.

14. The non-volatile storage apparatus of claim 10, wherein:

the plurality of non-volatile memory cells are arranged in a monolithic three dimensional memory structure;

the one or more control circuits include a controller and a state machine;

the controller is on a first die; and

the state machine and the monolithic three dimensional memory structure are on a second die.

15. A method for operating non-volatile storage, comprising:

receiving a request to read that includes an error indication;

performing a read process on the non-volatile storage to identify result data that includes a number of errors; and

returning the set of data with errors if the number of errors satisfies the error indication.

16. The method of claim 15, further comprising:

returning an error response without returning the set of data if the number of errors does not satisfy the error indication.

17. The method of claim 15, wherein:

the performing the read process includes attempting to correct errors in information sensed from the non-volatile storage and not being able to correct all errors in the information sensed from the non-volatile storage.

18. The method of claim 15, further comprising:

choosing an ECC read mode based on the error indication, the performing the read process includes performing error correction according to the chosen ECC read mode.

19. The method of claim 15, further comprising:

identifying one or more portions of the returned set of data that includes the errors if the number of errors satisfies the error indication.

20. The method of claim 15, wherein:

receiving a request to program that includes a quality indication; and

programming the non-volatile storage based on the received quality indication.

21. An apparatus, comprising:

non-volatile semiconductor memory; and

means for receiving a request to read that includes an operation limitation, performing a read process on the non-volatile semiconductor memory within the operation limitation and returning data from the read process that includes errors in response to the request to read.

22. An apparatus, comprising:

a host interface;

a memory interface; and

one or more processing circuits in communication with the host interface and the memory interface, the one or more processing circuits are configured to receive a request from a host via the host interface to read information stored in a non-volatile memory, the request includes a quality of service indication, the one or more processing circuits are configured to select an ECC read mode based on the quality of service indication, the one or more processing circuits are configured to perform a read process on the non-volatile memory via the memory interface that includes performing error correction according to the selected ECC read mode, the read process identifies a result set of data that includes errors, and the one or more processing circuits are configured to return the result set of data that includes errors to the host via the host interface in response to the request to read.

23. The apparatus of claim 22, wherein:

the one or more processing circuits include an ECC engine;

the one or more processing circuits are configured to select an ECC read mode for the ECC engine based on the quality of service indication; and

the read process includes the ECC engine performing error correction according to the selected ECC read mode.

24. The apparatus of claim 22, wherein:

the quality of service indication indicates an error threshold; and

the returned result set of data includes a number of errors less than the error threshold.