PROCESSOR-IN-MEMORY-AND-STORAGE ARCHITECTURE

• US 20180089025A1
• Filed: 11/28/2017
• Published: 03/29/2018
• Est. Priority Date: 08/20/2015
• Status: Active Grant

• Current Assignee: National Technology & Engineering Solutions Of Sandia LLC (Honeywell International Inc.)
• Original Assignee: National Technology & Engineering Solutions Of Sandia LLC (Honeywell International Inc.)
• Inventors: DeBenedictis, Erik
• Granted Patent: US 10,083,080 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 1/32 Means for saving power
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence

Abstract

A method and apparatus for performing reliable general-purpose computing. Each sub-core of a plurality of sub-cores of a processor core processes a same instruction at a same time. A code analyzer receives a plurality of residues that represents a code word corresponding to the same instruction and an indication of whether the code word is a memory address code or a data code from the plurality of sub-cores. The code analyzer determines whether the plurality of residues are consistent or inconsistent. The code analyzer and the plurality of sub-cores perform a set of operations based on whether the code word is a memory address code or a data code and a determination of whether the plurality of residues are consistent or inconsistent.

Claims

1. An apparatus comprising:

a memory array comprising a plurality of rows and a plurality of columns;

a switch that electrically connects to a particular row of the plurality of rows of the memory array per cycle; and

an energy storage unit that is electrically connected to the memory array through the switch.

2. The apparatus of claim 1, wherein the memory array, the switch, and the energy storage unit form an adiabatic memory circuit.

3. The apparatus of claim 1, wherein the switch allows a bi-directional flow of energy through the switch.

4. The apparatus of claim 1, wherein the energy storage unit is electrically connected in a series with an effective capacitance between ground and the particular row of the plurality of rows of the memory array to which the switch is connected to recycle energy from the memory array.