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OFFLOAD DATA TRANSFER ENGINE FOR A BLOCK DATA TRANSFER INTERFACE

  • US 20180089099A1
  • Filed: 09/29/2016
  • Published: 03/29/2018
  • Est. Priority Date: 09/29/2016
  • Status: Active Grant
First Claim
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1. A system, comprising:

  • at least one central processing unit;

    a memory having a destination memory which includes a first destination region configured to store a first block of data, and a second destination region configured to store a second block of data, wherein the memory further has a data structure memory configured to store an address map data structure to map a first logical address to a first physical address of the first destination region, a source memory configured to store a block of update data to update data of the first block of data, and a command set memory configured to store a data transfer command set from a central processing unit, the data transfer command set including at least one data transfer command from a central processing unit to transfer a block of data, from the source memory to the destination memory;

    a data path coupling the source memory to the destination memory wherein the data path bypasses the central processing unit;

    an offload data transfer engine configured to execute the data transfer command set, wherein the offload data transfer engine includes;

    data transfer logic, configured to be responsive to at least one command of the data transfer command set, to transfer the block of update data in the data path from the source memory to the second region of the destination memory, wherein the data path bypasses the central processing unit; and

    transfer status logic, configured to be responsive to at least one command of the data transfer command set to confirm successful transfer of the block of update data, and to provide a successful transfer indication of successful transfer of the block of update data to the second region; and

    address map update logic, configured to be responsive to the successful transfer indication, to re-map the first logical address to a second physical address of the second region of the destination memory, instead of the first physical address of the first region of the destination memory.

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