OFFLOAD DATA TRANSFER ENGINE FOR A BLOCK DATA TRANSFER INTERFACE

• US 20180089099A1
• Filed: 09/29/2016
• Published: 03/29/2018
• Est. Priority Date: 09/29/2016
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: RAJ, Ashok, RADHAKRISHNAN, Sivakumar, WILLIAMS, Dan J., VERMA, Vishal, RANGANATHAN, Narayan, DOUGLAS, Chet R.
• Granted Patent: US 10,157,142 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/10 Address translation
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/152 Virtualized environment, e.g. logically partitioned system
• CPC Class Codes: G06F 2212/65 Details of virtual memory and virtual address translation
• CPC Class Codes: G06F 3/0608 Saving storage space on storage systems
• CPC Class Codes: G06F 3/0631 by allocating resources to storage systems
• CPC Class Codes: G06F 3/0644 Management of space entities, e.g. partitions, extents, pools
• CPC Class Codes: G06F 3/0646 Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
• CPC Class Codes: G06F 3/0647 Migration mechanisms
• CPC Class Codes: G06F 3/065 Replication mechanisms
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0683 Plurality of storage devices

Abstract

In one embodiment, a block data transfer interface employing offload data transfer engine in accordance with the present description includes an offload data transfer engine executing a data transfer command set to transfer a block of data in a transfer data path from a source memory to a new region of a destination memory, wherein the transfer data path bypasses a central processing unit to minimize or reduce involvement of the central processing unit in the block transfer. In response to a successful transfer indication, a logical address is re-mapped to a physical address of the new region of the destination memory, instead of a physical address of the original region of the destination memory. In one embodiment, the re-mapping is performed by a central processing unit. In another embodiment, the re-mapping is performed by the offload data transfer engine. Other aspects are described herein.

Claims

1. A system, comprising:

at least one central processing unit;

a memory having a destination memory which includes a first destination region configured to store a first block of data, and a second destination region configured to store a second block of data, wherein the memory further has a data structure memory configured to store an address map data structure to map a first logical address to a first physical address of the first destination region, a source memory configured to store a block of update data to update data of the first block of data, and a command set memory configured to store a data transfer command set from a central processing unit, the data transfer command set including at least one data transfer command from a central processing unit to transfer a block of data, from the source memory to the destination memory;

a data path coupling the source memory to the destination memory wherein the data path bypasses the central processing unit;

an offload data transfer engine configured to execute the data transfer command set, wherein the offload data transfer engine includes;

data transfer logic, configured to be responsive to at least one command of the data transfer command set, to transfer the block of update data in the data path from the source memory to the second region of the destination memory, wherein the data path bypasses the central processing unit; and

transfer status logic, configured to be responsive to at least one command of the data transfer command set to confirm successful transfer of the block of update data, and to provide a successful transfer indication of successful transfer of the block of update data to the second region; and

address map update logic, configured to be responsive to the successful transfer indication, to re-map the first logical address to a second physical address of the second region of the destination memory, instead of the first physical address of the first region of the destination memory.

2. The system of claim 1 wherein the data structure memory is further configured to store a free region log data structure having entries to indicate free regions of the destination memory, the system further comprising log update logic configured to update an entry of a free region log data structure to indicate that the first region is available for use to store other data, after the first logical address is re-mapped to the second region of the destination memory.

3. The system of claim 1 wherein the address map data structure includes a block transfer table comprising entries wherein each block transfer table entry is configured to map a logical address to a physical address of the destination memory and wherein the address map update logic is further configured to be responsive to the successful transfer indication, to update a block transfer table entry to re-map the first logical address to a second physical address of the second region of the destination memory, instead of the first physical address of the first region of the destination memory.

4. The system of claim 3 wherein the address map update logic is further configured to acquire a block aperture region resource, program the block aperture region resource to point to an entry of the block transfer table, and perform an atomic write to the entry so that the first logical address is mapped to the second physical address of the second region of the destination memory, to update a block transfer table entry.

5. The system of claim 1 wherein the offload data transfer engine includes the address map update logic and wherein the data transfer command set includes at least one map data transfer command from a central processing unit to the offload data transfer engine, to initiate a transfer of map entry data by the offload data transfer engine, from a source memory to a data structure memory, wherein the address map update logic is configured to be responsive to the map data transfer command, to transfer the map entry data from a source memory to a data structure memory so that the first logical address is mapped to the second physical address of the second region of the destination memory.

6. The system of claim 2 wherein the offload data transfer engine includes the log update logic and wherein the data transfer command set includes at least one log data transfer command from a central processing unit to the offload data transfer engine, to initiate a transfer of free region log data structure entry data by the offload data transfer engine, from a source memory to a data structure memory wherein the log update logic is configured to be responsive to the log data transfer command, to transfer the free region log data structure entry data from a source memory to a data structure memory so that the updating causes the free region log to indicate that the first region is available for use to store other data.

7. The system of claim 1, wherein the offload data transfer engine further includes error handling logic configured to, in response to the data transfer command set:

detect an error in transferring data from the source memory to the destination memory; and

in response to error detection, stop the transfer of data from the source memory to the destination memory, provide a transfer failure indication of unsuccessful transfer of data to the destination memory, and leave the mapping of the first logical address to the first physical address of the first region of the destination memory unchanged.

8. The system of claim 2 wherein the offload data transfer engine includes the address map update logic and wherein the data transfer command set includes at least one map data transfer command from a central processing unit to the offload data transfer engine, to initiate a transfer of map entry data by the offload data transfer engine, from a source memory to a data structure memory, wherein the address map update logic is configured to be responsive to the map data transfer command and responsive to the successful transfer indication, to transfer the map entry data from a source memory to a data structure memory so that the first logical address is mapped to the second physical address of the second region of the destination memory;

wherein the offload data transfer engine further includes the log update logic and wherein the data transfer command set includes at least one log data transfer command from a central processing unit to the offload data transfer engine, to initiate a transfer of free region log data structure entry data by the offload data transfer engine, from a source memory to a data structure memory wherein the log update logic is configured to be responsive to the log data transfer command, to transfer the free region log data structure entry data from a source memory to a data structure memory so that the updating causes the free region log to indicate that the first region is available for use to store other data and

wherein the offload data transfer engine further includes error handling logic configured to, in response to the data transfer command set;

detect an error in transferring data from the source memory to a memory; and

in response to error detection, stop the transfer of data, provide a transfer failure indication of unsuccessful transfer of data, leave the mapping of the first logical address to the first physical address of the first region of the destination memory unchanged, and leave the free region log unchanged to indicate that the first region is unavailable for use to store other data.

9. A method, comprising:

forwarding a data transfer command set including at least one data transfer command from a central processing unit to an offload data transfer engine, to initiate a transfer by the offload data transfer engine of a block of data, from a source memory to a destination memory having first and second regions;

the offload data transfer engine executing the data transfer command set, including;

transferring the block of data in a transfer data path from the source memory to a second region of the destination memory, wherein the transfer data path bypasses the central processing unit; and

confirming successful transfer of the block of data, and providing a successful transfer indication of successful transfer of the block of data to the second region; and

in response to the successful transfer indication, re-mapping a first logical address to a physical address of the second region of the destination memory, instead of a physical address of the first region of the destination memory.

10. The method of claim 9 further comprising updating an entry of a free region log to indicate that the first region is available for use to store other data.

11. The method of claim 9 wherein the re-mapping includes updating a block transfer table comprising entries wherein each entry maps a logical address to a physical address of the destination memory.

12. The method of claim 11 wherein the updating a block transfer table includes acquiring a block aperture region resource, programming the block aperture region resource to point to an update entry of the block transfer table, performing an atomic write to the update entry so that the first logical address is mapped to the second physical address of the second region of the destination memory.

13. The method of claim 9 wherein the data transfer command set includes at least one data transfer command from a central processing unit to the offload data transfer engine, to initiate a transfer of map entry data by the offload data transfer engine, from a source memory to a destination memory so that the re-mapping includes the offload data transfer engine transferring the map entry data so that the first logical address is mapped to the second physical address of the second region of the destination memory.

14. The method of claim 10 wherein the data transfer command set includes at least one data transfer command from a central processing unit to the offload data transfer engine, to initiate a transfer of free region log entry data by the offload data transfer engine, from a source memory to a destination memory so that the updating an entry of a free region log causes the free region log to indicate that the first region is available for use to store other data.

15. The method of claim 9, further in response to the data transfer command set, the offload data transfer engine:

encountering an error in transferring data from the source memory to the destination memory; and

in response to encountering the error, stopping the transferring of data from the source memory to the destination memory, providing a transfer failure indication of unsuccessful transfer of data to the destination memory, and leaving the mapping of the first logical address to the first physical address of the first region of the destination memory unchanged.

16. The method of claim 9 wherein the data transfer command set further includes at least one data transfer command from a central processing unit to the offload data transfer engine, to initiate a transfer of map entry data by the offload data transfer engine, from a source memory to a destination memory so that the re-mapping includes the offload data transfer engine transferring the map entry data so that the first logical address is mapped to the second physical address of the second region of the destination memory, and at least one data transfer command from a central processing unit to the offload data transfer engine, to initiate a transfer of free region log entry data by the offload data transfer engine, from a source memory to a destination memory to update an entry of a free region log cause the free region log to indicate that the first region is available for use to store other data, and wherein further in response to the data transfer command set, the offload data transfer engine in response to encountering an error in transferring data from the source memory to the destination memory, aborts execution of the data transfer command set to stop the transfer of data from the source memory to the destination memory, and provides a transfer failure indication of unsuccessful transfer of data to the destination memory.

17. An apparatus for use with a central processing unit, comprising:

a memory having a destination memory which includes a first destination region configured to store a first block of data, and a second destination region configured to store a second block of data, wherein the memory further has a data structure memory configured to store an address map data structure to map a first logical address to a first physical address of the first destination region, a source memory configured to store a block of update data to update data of the first block of data, and a command set memory configured to store a data transfer command set from a central processing unit, the data transfer command set including at least one data transfer command from a central processing unit to transfer a block of data, from the source memory to the destination memory;

a data path coupling the source memory to the destination memory wherein the data path bypasses the central processing unit;

an offload data transfer engine configured to execute the data transfer command set, wherein the offload data transfer engine includes;

data transfer logic, configured to be responsive to at least one command of the data transfer command set, to transfer the block of update data in the data path from the source memory to the second region of the destination memory, wherein the data path bypasses the central processing unit; and

transfer status logic, configured to be responsive to at least one command of the data transfer command set to confirm successful transfer of the block of update data, and to provide a successful transfer indication of successful transfer of the block of update data to the second region; and

address map update logic, configured to be responsive to the successful transfer indication, to re-map the first logical address to a second physical address of the second region of the destination memory, instead of the first physical address of the first region of the destination memory.

18. The apparatus of claim 17 wherein the data structure memory is further configured to store a free region log data structure having entries to indicate free regions of the destination memory, the apparatus further comprising log update logic configured to update an entry of a free region log data structure to indicate that the first region is available for use to store other data, after the first logical address is re-mapped to the second region of the destination memory.

19. The apparatus of claim 17 wherein the address map data structure includes a block transfer table comprising entries wherein each block transfer table entry is configured to map a logical address to a physical address of the destination memory and wherein the address map update logic is further configured to be responsive to the successful transfer indication, to update a block transfer table entry to re-map the first logical address to a second physical address of the second region of the destination memory, instead of the first physical address of the first region of the destination memory.

20. The apparatus of claim 19 wherein the address map update logic is further configured to acquire a block aperture region resource, program the block aperture region resource to point to an entry of the block transfer table, and perform an atomic write to the entry so that the first logical address is mapped to the second physical address of the second region of the destination memory, to update a block transfer table entry.

21. The apparatus of claim 17 wherein the offload data transfer engine includes the address map update logic and wherein the data transfer command set includes at least one map data transfer command from a central processing unit to the offload data transfer engine, to initiate a transfer of map entry data by the offload data transfer engine, from a source memory to a data structure memory, wherein the address map update logic is configured to be responsive to the map data transfer command, to transfer the map entry data from a source memory to a data structure memory so that the first logical address is mapped to the second physical address of the second region of the destination memory.

22. The apparatus of claim 18 wherein the offload data transfer engine includes the log update logic and wherein the data transfer command set includes at least one log data transfer command from a central processing unit to the offload data transfer engine, to initiate a transfer of free region log data structure entry data by the offload data transfer engine, from a source memory to a data structure memory wherein the log update logic is configured to be responsive to the log data transfer command, to transfer the free region log data structure entry data from a source memory to a data structure memory so that the updating causes the free region log to indicate that the first region is available for use to store other data.

23. The apparatus of claim 17, wherein the offload data transfer engine further includes error handling logic configured to, in response to the data transfer command set:

detect an error in transferring data from the source memory to the destination memory; and

in response to error detection, stop the transfer of data from the source memory to the destination memory, provide a transfer failure indication of unsuccessful transfer of data to the destination memory, and leave the mapping of the first logical address to the first physical address of the first region of the destination memory unchanged.

24. The apparatus of claim 18 wherein the offload data transfer engine includes the address map update logic and wherein the data transfer command set includes at least one map data transfer command from a central processing unit to the offload data transfer engine, to initiate a transfer of map entry data by the offload data transfer engine, from a source memory to a data structure memory, wherein the address map update logic is configured to be responsive to the map data transfer command and responsive to the successful transfer indication, to transfer the map entry data from a source memory to a data structure memory so that the first logical address is mapped to the second physical address of the second region of the destination memory;

wherein the offload data transfer engine further includes the log update logic and wherein the data transfer command set includes at least one log data transfer command from a central processing unit to the offload data transfer engine, to initiate a transfer of free region log data structure entry data by the offload data transfer engine, from a source memory to a data structure memory wherein the log update logic is configured to be responsive to the log data transfer command, to transfer the free region log data structure entry data from a source memory to a data structure memory so that the updating causes the free region log to indicate that the first region is available for use to store other data and

wherein the offload data transfer engine further includes error handling logic configured to, in response to the data transfer command set;

detect an error in transferring data from the source memory to a memory; and

in response to error detection, stop the transfer of data, provide a transfer failure indication of unsuccessful transfer of data, leave the mapping of the first logical address to the first physical address of the first region of the destination memory unchanged, and leave the free region log unchanged to indicate that the first region is unavailable for use to store other data.