OFFLOAD DATA TRANSFER ENGINE FOR A BLOCK DATA TRANSFER INTERFACE
First Claim
1. A system, comprising:
- at least one central processing unit;
a memory having a destination memory which includes a first destination region configured to store a first block of data, and a second destination region configured to store a second block of data, wherein the memory further has a data structure memory configured to store an address map data structure to map a first logical address to a first physical address of the first destination region, a source memory configured to store a block of update data to update data of the first block of data, and a command set memory configured to store a data transfer command set from a central processing unit, the data transfer command set including at least one data transfer command from a central processing unit to transfer a block of data, from the source memory to the destination memory;
a data path coupling the source memory to the destination memory wherein the data path bypasses the central processing unit;
an offload data transfer engine configured to execute the data transfer command set, wherein the offload data transfer engine includes;
data transfer logic, configured to be responsive to at least one command of the data transfer command set, to transfer the block of update data in the data path from the source memory to the second region of the destination memory, wherein the data path bypasses the central processing unit; and
transfer status logic, configured to be responsive to at least one command of the data transfer command set to confirm successful transfer of the block of update data, and to provide a successful transfer indication of successful transfer of the block of update data to the second region; and
address map update logic, configured to be responsive to the successful transfer indication, to re-map the first logical address to a second physical address of the second region of the destination memory, instead of the first physical address of the first region of the destination memory.
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Abstract
In one embodiment, a block data transfer interface employing offload data transfer engine in accordance with the present description includes an offload data transfer engine executing a data transfer command set to transfer a block of data in a transfer data path from a source memory to a new region of a destination memory, wherein the transfer data path bypasses a central processing unit to minimize or reduce involvement of the central processing unit in the block transfer. In response to a successful transfer indication, a logical address is re-mapped to a physical address of the new region of the destination memory, instead of a physical address of the original region of the destination memory. In one embodiment, the re-mapping is performed by a central processing unit. In another embodiment, the re-mapping is performed by the offload data transfer engine. Other aspects are described herein.
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Citations
24 Claims
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1. A system, comprising:
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at least one central processing unit; a memory having a destination memory which includes a first destination region configured to store a first block of data, and a second destination region configured to store a second block of data, wherein the memory further has a data structure memory configured to store an address map data structure to map a first logical address to a first physical address of the first destination region, a source memory configured to store a block of update data to update data of the first block of data, and a command set memory configured to store a data transfer command set from a central processing unit, the data transfer command set including at least one data transfer command from a central processing unit to transfer a block of data, from the source memory to the destination memory; a data path coupling the source memory to the destination memory wherein the data path bypasses the central processing unit; an offload data transfer engine configured to execute the data transfer command set, wherein the offload data transfer engine includes; data transfer logic, configured to be responsive to at least one command of the data transfer command set, to transfer the block of update data in the data path from the source memory to the second region of the destination memory, wherein the data path bypasses the central processing unit; and transfer status logic, configured to be responsive to at least one command of the data transfer command set to confirm successful transfer of the block of update data, and to provide a successful transfer indication of successful transfer of the block of update data to the second region; and address map update logic, configured to be responsive to the successful transfer indication, to re-map the first logical address to a second physical address of the second region of the destination memory, instead of the first physical address of the first region of the destination memory. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method, comprising:
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forwarding a data transfer command set including at least one data transfer command from a central processing unit to an offload data transfer engine, to initiate a transfer by the offload data transfer engine of a block of data, from a source memory to a destination memory having first and second regions; the offload data transfer engine executing the data transfer command set, including; transferring the block of data in a transfer data path from the source memory to a second region of the destination memory, wherein the transfer data path bypasses the central processing unit; and confirming successful transfer of the block of data, and providing a successful transfer indication of successful transfer of the block of data to the second region; and in response to the successful transfer indication, re-mapping a first logical address to a physical address of the second region of the destination memory, instead of a physical address of the first region of the destination memory. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. An apparatus for use with a central processing unit, comprising:
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a memory having a destination memory which includes a first destination region configured to store a first block of data, and a second destination region configured to store a second block of data, wherein the memory further has a data structure memory configured to store an address map data structure to map a first logical address to a first physical address of the first destination region, a source memory configured to store a block of update data to update data of the first block of data, and a command set memory configured to store a data transfer command set from a central processing unit, the data transfer command set including at least one data transfer command from a central processing unit to transfer a block of data, from the source memory to the destination memory; a data path coupling the source memory to the destination memory wherein the data path bypasses the central processing unit; an offload data transfer engine configured to execute the data transfer command set, wherein the offload data transfer engine includes; data transfer logic, configured to be responsive to at least one command of the data transfer command set, to transfer the block of update data in the data path from the source memory to the second region of the destination memory, wherein the data path bypasses the central processing unit; and transfer status logic, configured to be responsive to at least one command of the data transfer command set to confirm successful transfer of the block of update data, and to provide a successful transfer indication of successful transfer of the block of update data to the second region; and address map update logic, configured to be responsive to the successful transfer indication, to re-map the first logical address to a second physical address of the second region of the destination memory, instead of the first physical address of the first region of the destination memory. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24)
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Specification