PRE-PROGRAMMED RESISTIVE CROSS-POINT ARRAY FOR NEURAL NETWORK

• US 20180089559A1
• Filed: 02/16/2017
• Published: 03/29/2018
• Est. Priority Date: 09/27/2016
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: International Business Machines Corporation
• Inventors: COPEL, MATTHEW W.
• Granted Patent: US 10,970,624 B2
• Time in Patent Office: Days
• CPC Class Codes: G06N 3/04 Architecture, e.g. interconnection topology
• CPC Class Codes: G06N 3/065 Analogue means
• CPC Class Codes: G06N 3/08 Learning methods
• CPC Class Codes: G06N 3/084 Backpropagation, e.g. using gradient descent
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10N 70/063 by etching of pre-deposited switching material layers, e.g. lithography
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/881 Switching materials

Abstract

Technical solutions are described for forming a semiconductor device for a crosspoint array that implements a pre-programmed neural network. An example method includes sequentially depositing a semiconducting layer, a top insulating layer, and a shunting layer onto a base insulating layer. The method further includes etching selective portions of the top insulating layer corresponding to resistance values associated with weights of the crossbar that implements the neural network.

Claims

1. A semiconductor device comprising:

a semiconducting layer deposited on a base insulating layer;

a top insulating layer deposited on the semiconducting layer;

a portion of the top insulating layer removed; and

a shunting layer deposited on the top insulating layer, wherein the shunting layer contacts the semiconducting layer via the portion that is removed from the top insulating layer, wherein dimensions of the portion determine a resistance value of the semiconductor device.

2. The semiconductor device of claim 1, further comprising, wherein a selective portion of the shunting layer is etched, wherein the selective portion that is etched from the shunting layer is associated with the portion removed from the insulating layer.

3. The semiconductor device of claim 1, wherein the insulating layer comprises a dielectric material that is selected from a group consisting of aluminum oxide (Al₂O₃), magnesium oxide (MgO), boron nitride (BN), silicon oxynitride (SiO_xN_y), and silicon oxide (SiO₂).

4. The semiconductor device of claim 1, wherein the shunting layer is deposited by using a self-aligned configuration, wherein the shunting layer comprises shunting material that reacts with semiconducting material of the semiconducting layer in response to applying heat.

5. The semiconductor device of claim 1, wherein a shunting material for the shunting layer is selected from a group consisting of silicides of titanium, nickel, cobalt, and platinum, and germanides of titanium, nickel, cobalt, and platinum.

6. The semiconductor device of claim 5, wherein the shunting layer is deposited in a patterned manner by using a lithographic process.

7. A semiconductor device comprising:

sequentially deposited layers on a base insulating layer, the sequentially deposited layers comprising a semiconducting layer, a top insulating layer, and a shunting layer; and

wherein, selective portions of the top insulating layer are etched corresponding to resistance values associated with weights of a crossbar that implements a neural network.

8. The semiconductor device of claim 7, wherein a selective portion of the shunting layer is etched, wherein the selective portion that is etched from the shunting layer is associated with the portion removed from the top insulating layer.

9. The semiconductor device of claim 7, wherein the top insulating layer comprises a dielectric material that is selected from a group consisting of aluminum oxide (Al₂O₃), magnesium oxide (MgO), boron nitride (BN), silicon oxynitride (SiO_xN_y), and silicon oxide (SiO₂).

10. The semiconductor device of claim 7, wherein the shunting layer is deposited by using a self-aligned configuration, wherein the shunting layer comprises shunting material that reacts with semiconducting material of the semiconducting layer.

11. The semiconductor device of claim 10, wherein a shunting material of the shunting layer reacts with the semiconducting material in response to applying heat.

12. The semiconductor device of claim 10, wherein a shunting material for the shunting layer is selected from a group consisting of silicides of titanium, nickel, cobalt, and platinum, and germanides of titanium, nickel, cobalt, and platinum.

13. The semiconductor device of claim 7, wherein the shunting layer is deposited in a patterned manner by using a lithographic process.