MEMORY DEVICE AND OPERATING METHOD THEREOF

• US 20180090217A1
• Filed: 06/21/2017
• Published: 03/29/2018
• Est. Priority Date: 09/29/2016
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: PARK, Hyun Kyu
• Granted Patent: US 10,586,603 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region

Abstract

There are provided a memory device and an operating method thereof. A memory device may include a memory block, peripheral circuits, and a control logic. The memory block may include a plurality of memory cells. The peripheral circuits may perform a program operation on the memory cells. The control logic may control the peripheral circuits to apply, during the program operation, a program voltage to a selected word line and selectively apply, to one or more unselected word lines, a second pass voltage lower than a first pass voltage set as a default voltage during a blind program period which does not include a verify operation.

Claims

1. A memory device comprising:

a memory block including a plurality of memory cells;

peripheral circuits configured to perform a program operation on the memory cells; and

a control logic configured to control the peripheral circuits to apply, during the program operation, a program voltage to a selected word line and selectively apply, to one or more unselected word lines, a second pass voltage lower than a first pass voltage set as a default voltage during a blind program period which does not include a verify operation.

2. The memory device of claim 1, wherein the peripheral circuits include a voltage generation circuit configured to generate the program voltage, a verify voltage, the first pass voltage, and the second pass voltage being a positive voltage lower than the first pass voltage, which are used in the program operation.

3. The memory device of claim 2, wherein the voltage generation circuit generates the second pass voltage to be gradually increased.

4. The memory device of claim 1, wherein the control logic controls the peripheral circuits to, during the blind program period, apply the first pass voltage to unselected word lines adjacent to the selected word line and apply the second pass voltage to the other unselected word lines.

5. The memory device of claim 1, wherein, during a normal program period, threshold voltages of the memory cells increase by applying the program voltage to the selected word line and the verify operation are performed by applying a verify voltage to the selected word line and by applying the first pass voltage to unselected word lines adjacent to the selected word line and the other unselected word lines.

6. The memory device of claim 1, wherein the memory block is formed in a three-dimensional structure in which the memory cells are stacked in a vertical direction.

7. The memory device of claim 6, wherein the selected word line is a word line coupled to selected memory cells among the memory cells, and the adjacent word lines are word lines that are immediately adjacent the selected word line.

8. The memory device of claim 1, wherein, during the blind program period, a plurality of program voltage pulses is consecutively applied to the selected word line.

9. A method of operating a memory device, the method comprising, during a blind program period during which a program voltage is applied to a selected word line without performing a verify operation, applying a second pass voltage lower than a first pass voltage set as a default voltage to one or more unselected word lines.

10. The method of claim 9, wherein the second pass voltage is a positive voltage lower than the first pass voltage.

11. The method of claim 9, wherein, during the blind program period, the program voltage being applied to the selected word line gradually increases.

12. The method of claim 9, wherein the time required to perform the blind program period is adjusted depending on memory devices.

13. The method of claim 9, wherein, during the blind program period, a plurality of program voltage is consecutively applied to the selected word line.

14. A method of operating a memory device, the method comprising:

determining whether a program operation set to be performed includes a blind program period in which a program voltage is applied to a selected word line without performing a verify operation, in response to a program command; and

when the program operation includes a blind program period, programming selected memory cells by applying the program voltage to the selected word line and applying a second pass voltage lower than a first pass voltage set as a default voltage to unselected word lines.

15. The method of claim 14, wherein, in determining whether the program operation includes the blind program period:

it is determined that, if the program command is a blind program command, the program operation includes the blind program period; and

it is determined that, if the program command is a normal program command, the program operation does not include the blind program period.

16. The method of claim 15, wherein, if the program command is the blind program command, the program operation includes the blind program period and a normal program period.

17. The method of claim 16, wherein, during the normal program period, threshold voltages of the selected memory cells are increased by applying the program voltage to the selected word line, and a verify operation is performed to determine whether the threshold voltages of the selected memory cells have been reached target voltages.

18. The method of claim 15, wherein, if the program command is the normal program command, threshold voltages of the selected memory cells are increased by applying the program voltage to the selected word line, and a verify operation is performed to determine whether the threshold voltages of the selected memory cells have been reached target voltages.

19. The method of claim 14, further comprising, before determining whether the program operation includes the blind program period, setting up various voltages to be used in the program operation in response to the program command.

20. The method of claim 19, wherein the various voltages include the program voltage, the first pass voltage, the second pass voltage, and a verify voltage.