Stacked Backside Illuminated SPAD Array

• US 20180090536A1
• Filed: 09/22/2017
• Published: 03/29/2018
• Est. Priority Date: 09/23/2016
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Mandai, Shingo, Niclass, Cristiano L., Karasawa, Nobuhiro, Fan, Xiaofeng, Laflaquiere, Arnaud, Agranov, Gennadiy A.
• Granted Patent: US 10,438,987 B2
• Time in Patent Office: Days
• CPC Class Codes: G01S 7/4861 Circuits for detection, sampling, integration or read-out
• CPC Class Codes: G01S 7/4863 Detector arrays, e.g. charge-transfer gates
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/1461 characterised by the photosensitive area
• CPC Class Codes: H01L 27/14616 characterised by the channel of the transistor, e.g. channel having a doping gradient
• CPC Class Codes: H01L 27/14623 Optical shielding
• CPC Class Codes: H01L 27/14627 Microlenses
• CPC Class Codes: H01L 27/14629 Reflectors
• CPC Class Codes: H01L 27/1463 Pixel isolation structures
• CPC Class Codes: H01L 27/14632 Wafer-level processed structures
• CPC Class Codes: H01L 27/14634 Assemblies, i.e. Hybrid structures
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/14665 Imagers using a photoconductor layer
• CPC Class Codes: H01L 31/02027 for devices working in avalanche mode
• CPC Class Codes: H01L 31/03529 Shape of the potential jump barrier or surface barrier
• CPC Class Codes: H01L 31/107 the potential barrier working in avalanche mode, e.g. avalanche photodiodes
• CPC Class Codes: H04N 25/587 acquired sequentially, e.g. using the combination of odd and even image fields
• CPC Class Codes: H04N 25/617 for reducing electromagnetic interference, e.g. clocking noise
• CPC Class Codes: H04N 25/709 : Circuitry for control of the power supply
• CPC Class Codes: H04N 25/745 : Circuitry for generating timing or clock signals
• CPC Class Codes: H04N 25/75 : Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/771 : comprising storage means other than floating diffusion

Abstract

A back-illuminated single-photon avalanche diode (SPAD) image sensor includes a sensor wafer stacked vertically over a circuit wafer. The sensor wafer includes one or more SPAD regions, with each SPAD region including an anode gradient layer, a cathode region positioned adjacent to a front surface of the SPAD region, and an anode avalanche layer positioned over the cathode region. Each SPAD region is connected to a voltage supply and an output circuit in the circuit wafer through inter-wafer connectors. Deep trench isolation elements are used to provide electrical and optical isolation between SPAD regions.

Claims

1. A back-illuminated single-photon avalanche diode (SPAD) image sensor, comprising:

a sensor wafer, comprising;

an SPAD region, comprising;

an anode gradient layer comprising a first dopant type;

a cathode region positioned adjacent to a front surface of the SPAD region and comprising a second dopant type; and

an anode avalanche layer positioned over the cathode region and comprising the first dopant type;

wherein;

the cathode region has a first area and the anode avalanche layer has a second area that is less than the first area; and

a dopant concentration of the first dopant type in the anode gradient layer is higher at a back surface of the sensor wafer and lower at a front surface of the anode gradient layer to produce a dopant concentration gradient in the anode gradient layer that guides a photon-generated charge carrier through the anode gradient layer to the anode avalanche layer; and

a circuit wafer positioned below and attached to the sensor wafer.

2. The back-illuminated SPAD image sensor of claim 1, wherein the circuit wafer comprises:

a voltage supply coupled to the SPAD region through a first inter-wafer connector; and

an output circuit coupled to the cathode region through a second inter-wafer connector;

wherein the voltage supply is configured to supply a high voltage to the SPAD region to provide a reverse bias across the cathode region and the anode gradient layer.

3. The back-illuminated SPAD image sensor of claim 2, further comprising a deep trench isolation region adjacent to the SPAD region, the deep trench isolation region extending from the front surface of the SPAD region to and through the back surface of the sensor wafer.

4. The back-illuminated SPAD image sensor of claim 3, further comprising a pinning layer comprising the first dopant type and extending along an exterior surface of the deep trench isolation region from the back surface of the sensor wafer to the front surface of the SPAD region, the pinning layer connecting to the first inter-wafer connector.

5. The back-illuminated SPAD image sensor of claim 4, wherein the voltage supply is configured to provide an isolation voltage to the pinning layer through the first inter-wafer connector.

6. The back-illuminated SPAD image sensor of claim 5, further comprising a doped well adjacent to the exterior surface of the deep trench isolation region at the front surface of the SPAD region and comprising the first dopant type, the doped well connecting to the pinning layer and to the first inter-wafer connector.

7. The back-illuminated SPAD image sensor of claim 6, wherein the voltage supply is configured to provide the isolation voltage to the doped well through the first inter-wafer connector.

8. The back-illuminated SPAD image sensor of claim 6, further comprising a diffusion region adjacent to the exterior surface of the deep trench isolation region and the front surface of the SPAD region and comprising the first dopant type, the diffusion region connecting to the doped well.

9. The back-illuminated SPAD image sensor of claim 3, further comprising a light shield disposed on the back surface of the sensor wafer over the deep trench isolation region.

10. The back-illuminated SPAD image sensor of claim 1, wherein a lateral shield extends laterally below at least a portion of the SPAD region to reflect photons back to the SPAD region.

11. The back-illuminated SPAD image sensor of claim 1, wherein the anode avalanche layer has a doping level so that it is depleted of charge carriers at an applied reverse bias voltage before a breakdown voltage of a junction of the anode avalanche layer with the cathode region.

12. An electronic device, comprising:

a back-illuminated single-photon avalanche diode (SPAD) image sensor, comprising;

a sensor wafer, comprising;

a first SPAD region and a second SPAD region adjacent to the first SPAD region, the first and the second SPAD regions each comprising;

an anode gradient layer comprising a first dopant;

a cathode region comprising a second dopant and adjacent to a front surface of the SPAD region;

an anode avalanche layer comprising the first dopant and positioned over the cathode region; and

a deep trench isolation region positioned between the first SPAD region and the second SPAD region, the deep trench isolation region extending through a back surface of the sensor wafer; and

a circuit wafer attached to the front surface of the sensor wafer; and

a processing device operably connected to the back-illuminated SPAD image sensor and configured to;

receive output signals from the back-illuminated SPAD image sensor; and

determine time-of-flight data based on the output signals.

13. The electronic device of claim 12, wherein the circuit wafer comprises:

a voltage supply coupled to the first SPAD region through a first inter-wafer connector and to the second SPAD region through a second inter-wafer connector, the voltage supply configured to provide a high reverse bias voltage level to the first and second SPAD regions; and

an output circuit coupled to a respective cathode region through a third inter-wafer connector.

14. The electronic device of claim 13, wherein the deep trench isolation region comprises:

a via; and

a conductive material disposed in the via.

15. The electronic device of claim 14, wherein the conductive material is connected to the voltage supply through a fourth inter-wafer connector, the voltage supply further configured to provide an isolation voltage to the conductive material.

16. The electronic device of claim 12, wherein the deep trench isolation region comprises:

a via; and

an insulating material disposed in the via.

17. The electronic device of claim 12, wherein the deep trench isolation region comprises:

a via; and

alternating layers of a low refractive index material and a high refractive index material.

18. The electronic device of claim 12, further comprising a passivation layer positioned over an exterior surface of the deep trench isolation region.

19. The electronic device of claim 12, further comprising:

a pinning layer positioned over an exterior surface of the deep trench isolation region and comprising the first dopant; and

a doped well positioned over a portion of the exterior surface of the deep trench isolation region adjacent to the front surface of the anode gradient layer and comprising the first dopant, wherein the doped well is connected to the pinning layer.

20. A back-illuminated single-photon avalanche diode (SPAD) image sensor, comprising:

a sensor wafer, comprising;

an array of SPAD regions, each SPAD region comprising;

an anode gradient layer comprising a first dopant type configured in a dopant concentration gradient, the dopant concentration gradient having a higher dopant concentration adjacent to a back surface of the sensor wafer and a lower dopant concentration adjacent to a front surface of the SPAD region;

a cathode region comprising a second dopant type and positioned adjacent to the front surface of the SPAD region, the cathode region having a first area; and

an anode avalanche layer comprising the first dopant type and positioned over the cathode region, the anode avalanche layer having a second area that is less than the first area;

a deep trench isolation region adjacent to each SPAD region in the array of SPAD regions;

a light shield positioned over the deep trench isolation region;

a passivation layer positioned over an exterior surface of the deep trench isolation regions; and

a light reflector positioned below at least a portion of each SPAD region; and

a circuit wafer positioned below and attached to the sensor wafer.

21. The back-illuminated SPAD image sensor of claim 20, wherein the deep trench isolation region comprises:

a via; and

alternating layers of a low refractive index material and a high refractive index material.