FORMING A SACRIFICIAL LINER FOR DUAL CHANNEL DEVICES
First Claim
Patent Images
1. A semiconductor device, comprising:
- one or more fins, each fin comprising;
a top channel portion formed from a channel material; and
a bottom substrate portion formed from a same material as an underlying substrate, the top channel portion having a different width than the bottom substrate portion;
an isolation dielectric layer fowled between and around the bottom substrate portion of the one or more fins;
an oxide layer formed between the bottom substrate portion of each fin and the isolation dielectric layer, wherein a space exists between a sidewall of at least a top portion of the oxide layer and an adjacent sidewall of the one or more fins; and
a gate dielectric formed over the one or more fins and in the space.
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Abstract
Semiconductor devices include one or more fins. Each fin includes a top channel portion formed from a channel material and a bottom substrate portion formed from a same material as an underlying substrate, the top channel portion having a different width than the bottom substrate portion. An isolation dielectric layer formed between and around the bottom substrate portion of the one or more fins. A space exists between at least a top portion of the isolation dielectric layer and the one or more fins. A gate dielectric is formed over the one or more fins and in the space.
8 Citations
20 Claims
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1. A semiconductor device, comprising:
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one or more fins, each fin comprising; a top channel portion formed from a channel material; and a bottom substrate portion formed from a same material as an underlying substrate, the top channel portion having a different width than the bottom substrate portion; an isolation dielectric layer fowled between and around the bottom substrate portion of the one or more fins; an oxide layer formed between the bottom substrate portion of each fin and the isolation dielectric layer, wherein a space exists between a sidewall of at least a top portion of the oxide layer and an adjacent sidewall of the one or more fins; and a gate dielectric formed over the one or more fins and in the space. - View Dependent Claims (2, 3, 4, 5, 7, 8, 9)
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6. (canceled)
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10. A semiconductor device, comprising:
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one or more fins, each fin comprising; a top channel portion formed from a channel material; and a bottom substrate portion formed from a same material as an underlying substrate, wherein a top channel portion of each of the one or more fins has a width that is lower than a width of the bottom substrate portion of each respective fin; an isolation dielectric layer formed between and around the bottom substrate portion of the one or more fins; an oxide layer formed between the bottom substrate portion of each fin and the isolation dielectric layer, wherein a space exists between a sidewall of at least a top portion of the oxide layer and an adjacent sidewall the one or more fins; and a gate dielectric formed over the one or more fins and in the space. - View Dependent Claims (11, 12, 13, 15, 16, 17)
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14. (canceled)
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18. A semiconductor device, comprising:
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one or more fins, each fin comprising; a top channel portion formed from a channel material; a bottom substrate portion formed from a same material as an underlying substrate, wherein the top channel portion of each of the one or more fins has a width that is lower than a width of the bottom substrate portion of each respective fin; and a middle portion formed from a same material as the underlying substrate and having a width that is lower than the width of the bottom substrate portion; an isolation dielectric layer formed between and around the bottom substrate portion of the one or more fins; an oxide layer formed between the bottom substrate portion of each fin and the isolation dielectric layer, wherein a space exists between a sidewall of at least a top portion of the oxide layer and an adjacent sidewall of the one or more fins; and a gate dielectric formed over the one or more fins and in the space. - View Dependent Claims (19, 20)
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Specification