THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF

• US 20180090620A1
• Filed: 09/25/2017
• Published: 03/29/2018
• Est. Priority Date: 09/29/2016
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: MOROSAWA, Narihiro
• Granted Patent: US 10,804,404 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/02175 characterised by the metal H01L21/02197 takes precedence
• CPC Class Codes: H01L 21/02178 the material containing aluminium, e.g. Al2O3
• CPC Class Codes: H01L 21/02181 the material containing hafnium, e.g. HfO2
• CPC Class Codes: H01L 21/02186 the material containing titanium, e.g. TiO2
• CPC Class Codes: H01L 21/02189 the material containing zirconium, e.g. ZrO2
• CPC Class Codes: H01L 21/02194 the material containing more than one metal element
• CPC Class Codes: H01L 21/02244 of a metallic layer
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1262 with a particular formation, treatment or coating of the substrate
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs

Abstract

A thin film transistor array panel includes an oxide semiconductor layer disposed on a substrate and includes a source region, a drain region, and a channel region, a gate insulating layer and a gate electrode disposed on the oxide semiconductor layer, source region, and a drain region, a first passivation layer disposed on the gate electrode, a second passivation layer disposed on the first passivation layer, and a source electrode and a drain electrode disposed on the second passivation, and the source electrode is connected with the source region, the drain electrode is connected with the drain region, the first passivation layer and the second passivation layer include the same metal oxide, and an amount of metal included in the first passivation layer is different from an amount of metal included in the second passivation layer.

Claims

1. A thin film transistor array panel comprising:

an oxide semiconductor layer disposed on a substrate and comprises a source region, a drain region, and a channel region;

a gate insulating layer and a gate electrode disposed on the oxide semiconductor layer;

a first passivation layer disposed on the gate electrode, the source region, and the drain region;

a second passivation layer disposed on the first passivation layer; and

a source electrode and a drain electrode disposed on the second passivation layer, the source electrode being connected with the source region and the drain electrode being connected with the drain region,

wherein the first passivation layer and the second passivation layer comprise the same metal oxide, and

an amount of metal included in the first passivation layer is different from an amount of metal included in the second passivation layer.

2. The thin film transistor array panel of claim 1, wherein the first passivation layer and the second passivation layer respectively comprise an aluminum oxide, and an amount of aluminum included in the first passivation layer is smaller than an amount of aluminum included in the second passivation layer.

3. The thin film transistor array panel of claim 1, wherein the first passivation layer and the second passivation layer respectively have a thickness of about less than 10 nanometers.

4. The thin film transistor array panel of claim 1, further comprising an interlayer insulation layer disposed between the first passivation layer and the second passivation layer, and comprises at least one of a silicon oxide (SiOx), a silicon nitride (SiNx), and a silicon oxynitride (SiON).

5. A thin film transistor array panel comprising:

an oxide semiconductor layer disposed on a substrate and includes a source region, a drain region, and a channel region;

a gate insulating layer and a gate electrode disposed on the oxide semiconductor layer;

a first passivation layer disposed on the gate electrode, the source region, and the drain region;

a second passivation layer disposed on the first passivation layer; and

a source electrode and a drain electrode disposed on the second passivation layer, the source electrode being connected with the source region and the drain electrode being connected with the drain region,

wherein the first passivation layer and the second passivation layer comprise different metal oxides, and

the first passivation layer comprises hydrogen.

6. The thin film transistor array panel of claim 5, wherein the first passivation layer comprises at least one of a titanium oxide and a zirconium oxide.

7. The thin film transistor array panel of claim 5, wherein the second passivation layer comprises an aluminum oxide.

8. The thin film transistor array panel of claim 5, wherein the first passivation layer and the second passivation layer respectively have a thickness of about less than 10 nanometers.

9. The thin film transistor array panel of claim 5, further comprising an interlayer insulation layer which is disposed between the first passivation layer and the second passivation layer, and comprises at least one of a silicon oxide (SiOx), a silicon nitride (SiNx), and a silicon oxynitride (SiON).

10. A thin film transistor array panel comprising;

an oxide semiconductor layer disposed on a substrate and includes a source region, a drain region, and a channel region;

a gate insulating layer and a gate electrode disposed on the oxide semiconductor layer;

a first passivation layer disposed on the gate electrode, the source region, and the drain region; and

a source electrode and a drain electrode disposed on the first passivation layer, the source electrode being connected with the source region and the drain electrode being connected with the drain region,

wherein the first passivation layer comprises at least one of an aluminum oxide, a zirconium oxide, a titanium oxide, a magnesium oxide, a hafnium oxide, a titanium aluminum oxide, and an aluminum magnesium oxide, and a thickness of the first passivation layer is about 10 nanometers or more.

11. A method for manufacturing a thin film transistor array panel, comprising:

forming an oxide semiconductor pattern on a substrate;

forming a gate insulating layer and a gate electrode on the oxide semiconductor pattern;

forming a first passivation layer by stacking a first metal layer on the gate electrode and the oxide semiconductor pattern and oxidizing the first metal layer;

forming a second passivation layer by stacking a second metal layer on the first passivation layer and oxidizing the second metal layer; and

forming a source electrode and a drain electrode on the second passivation layer,

wherein

a source region and a drain region are formed in areas, which contact the first metal layer, of the oxide semiconductor pattern in the oxidization of the first metal layer,

the first passivation layer and the second passivation layer comprise the same metal oxide, and an amount of metal included in the first passivation layer is different from an amount of metal included in the second passivation layer, and

the source electrode is connected with the source region and the drain electrode is connected with the drain region.

12. The method for manufacturing the thin film transistor array panel of claim 11, wherein the first passivation layer and the second passivation layer respectively comprise an aluminum oxide, and an amount of metal included in the first passivation layer is smaller than an amount of metal included in the second passivation layer.

13. The method for manufacturing the thin film transistor array panel of claim 11, wherein the first metal layer and the second metal layer respectively have a thickness of about less than 10 nm.

14. The method for manufacturing the thin film transistor array panel of claim 11, further comprising forming an interlayer insulation layer between the first passivation layer and the second passivation layer.

15. A method for manufacturing a thin film transistor array panel, comprising:

forming an oxide semiconductor pattern on a substrate;

forming a gate insulating layer and a gate electrode on the oxide semiconductor pattern;

forming a first passivation layer by stacking a first metal layer on the gate electrode and the oxide semiconductor pattern and oxidizing the first metal layer;

forming a second passivation layer by stacking a second metal layer on the first metal layer and oxidizing the second metal layer; and

forming a source electrode and a drain electrode on the second passivation layer,

wherein

a source region and a drain region are formed in areas, which contact the first metal layer, of the oxide semiconductor pattern in the oxidization of the first metal layer, and

the first passivation layer and the second passivation layer comprise different metal oxides, and the first passivation layer further comprises hydrogen, and

the source electrode is connected with the source region and the drain electrode is connected with the drain region.

16. The method for manufacturing the thin film transistor array panel of claim 15,

wherein

the second metal layer is stacked on the first metal layer after stacking the first metal layer, and

the first passivation layer and the second passivation layer are respectively formed by simultaneously oxidizing the first metal layer and the second metal layer.

17. The method for manufacturing the thin film transistor array panel of claim 15,

wherein

the first passivation layer comprises at least one of a titanium oxide and a zirconium oxide, and

the second passivation layer comprises an aluminum oxide.

18. The method for manufacturing the thin film transistor array panel of claim 15, wherein the first passivation layer and the second passivation layer respectively have a thickness of about less than 10 nanometers.

19. The method for manufacturing the thin film transistor array panel of claim 15, further comprising forming an interlayer insulation layer between the first passivation layer and the second passivation layer.

20. A method for manufacturing a thin film transistor array panel, comprising;

forming an oxide semiconductor pattern on a substrate;

forming a gate insulating layer and a gate electrode on the oxide semiconductor pattern;

forming a first passivation layer by stacking a first metal layer on the gate electrode and oxide semiconductor pattern and oxidizing the first metal layer; and

forming a source electrode and a drain electrode on the first passivation layer,

wherein

a source region and a drain region are formed in areas, which contact the first metal layer, of the oxide semiconductor pattern in the oxidization of the first metal layer, and

the first passivation layer comprises at least one of an aluminum oxide, a zirconium oxide, a titanium oxide, a magnesium oxide, a hafnium oxide, a titanium aluminum oxide, and an aluminum magnesium oxide, and a thickness of the first passivation layer is about 10 nanometers or more, and

the source electrode is connected with the source region and the drain electrode is connected with the drain region.