Power supply voltage monitoring and high-resolution adaptive clock stretching circuit

• US 20180091125A1
• Filed: 09/28/2016
• Published: 03/29/2018
• Est. Priority Date: 09/28/2016
• Status: Active Grant

• Current Assignee: Mellanox Technologies Limited (NVIDIA Corporation)
• Original Assignee: Mellanox Technologies Limited (NVIDIA Corporation)
• Inventors: Carlson, Andrew, Ramey, Carl
• Granted Patent: US 10,148,258 B2
• Time in Patent Office: Days
• CPC Class Codes: G01R 31/31725 Timing aspects, e.g. clock distribution, skew, propagation delay for tester hardware G01R31/31937
• CPC Class Codes: G06F 1/3206 Monitoring of events, devices or parameters that trigger a change in power modality
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: H03K 5/06 by the use of delay lines or other analogue delay elements
• CPC Class Codes: H03K 5/135 by the use of time reference signals, e.g. clock signals
• CPC Class Codes: H03K 5/19 Monitoring patterns of pulse trains indicating amplitude G01R19/00; indicating frequency G01R23/00; measuring characteristics of individual pulses G01R29/02

Abstract

An integrated circuit and method are described for compensating for voltage droop on an integrated circuit using a power supply voltage monitoring circuit and a high-resolution adaptive clock stretching circuit. In some example embodiments, the method includes monitoring power supply voltage on an integrated circuit, detecting a voltage droop such as a dynamic loss of power supply in the integrated circuit, and stretching a current clock cycle, according to the detected voltage droop, to provide more time for logic on the integrated circuit to complete before a next clock cycle.

Claims

1. An integrated circuit comprising:

a delay chain system comprising;

a plurality of delay chains, wherein each delay chain comprises a delay chain path and each delay chain path comprises a different length;

a controlled set of capture flops configured to sample each delay chain path every clock cycle to determine if the logic in the delay chain path completed during each clock cycle; and

an adder configured to sum the number of delay chain paths determined to have passed each clock cycle;

a filter configured to filter the sum of the number of delay chain paths determined to have passed each clock cycle;

a clock phase generator and validator, configured to generate a plurality of independent clock phases and configured to determine a plurality of valid clock phases; and

a clock phase multiplexer configured to shift from a current clock phase to a next clock phase selected from the plurality of valid clock phases.

2. The integrated circuit of claim 1, wherein the delay chain system further comprises a synchronizer configured to synchronize the sampled values from the delay chain path prior to summing the number of paths passing.

3. The integrated circuit of claim 1, wherein the filter configured to filter the sum of the number of delay chain paths determined to have passed each clock cycle is configured as a Kalman Filter.

4. A method for handling voltage droop on an integrated circuit comprising:

monitoring power supply voltage in the integrated circuit;

detecting a voltage droop comprising a dynamic loss of power supply in the integrated circuit; and

stretching a current clock cycle, according to the detected voltage droop, to provide more time for logic on the integrated circuit to complete before a next clock cycle.

5. The method according to claim 4, wherein monitoring supply voltage on the integrated circuit further comprises:

running a plurality of delay chains in the integrated circuit, wherein the plurality of delay chains comprises individual delay chain paths, each delay chain path comprising a different length;

sampling each of the plurality of delay chain paths every clock cycle, wherein each delay chain path is sampled during a current clock cycle from a controlled set of capture flops to determine if the logic in the delay chain path completed during the current cycle; and

summing a number of valid delay chain paths to obtain a variable output sum, wherein valid delay chain paths comprise delay chain paths whose logic completed in the current cycle, and wherein the variable output sum is a representation of the power supply voltage level during each clock cycle.

6. The method of claim 5, wherein monitoring supply voltage in the integrated circuit further comprises prior, to summing valid delay chain paths to obtain the variable output sum, synchronizing an output of each of the plurality of delay chain paths to prevent errors in the variable output sum due to metastability in the delay chain paths.

7. The method of claim 5, wherein detecting the voltage droop in the integrated circuit further comprises:

filtering the variable output sum to reduce a difference between the output sum representation of the power supply voltage level and the actual supply voltage level experienced on the integrated circuit, wherein the difference is caused by circuit noise; and

determining from the filtered variable output sum the voltage droop on the integrated circuit.

8. The method of claim 7, wherein filtering the variable output sum further comprises utilizing a Kalman filter.

9. The method of claim 4, wherein, stretching the current clock cycle further comprises:

generating a plurality of independent clock phases, wherein each of the plurality of clock phases comprises a rising edge, and wherein the plurality of independent clock phases together form a distribution of clock phases, wherein the rising edges of the plurality of clock phases in the distribution are offset by a uniform time interval;

determining a number of valid clock phases, wherein a valid clock phase comprises a clock phase comprising a rising edge which occurs before the rising edge of a current clock phase;

determining a next clock phase from the number of valid clock phases based on the detected voltage droop, wherein the next clock phase comprises a next clock rate which will allow the integrated circuit to complete all circuits in the next clock rate cycle; and

shifting from the current clock phase to the next clock phase.

10. The method of claim 9, wherein determining a next clock phase further comprises:

determining from the valid clock phases a plurality of clock phases that are not delayed more than half a clock cycle from the current clock phase, and determining the next clock phase from the determined plurality of clock phases.

11. The method according to claim 4, further comprising:

monitoring supply voltage in the integrated circuit during the detected voltage droop;

detecting a recovery of supply voltage during the detected voltage droop; and

dynamically adjusting the clock rate, according to the recovered supply voltage, to increase the clock rate.