TERMINAL STATION APPARATUS, BASE STATION APPARATUS, TRANSMISSION METHOD AND CONTROL METHOD

• US 20180091247A1
• Filed: 11/17/2017
• Published: 03/29/2018
• Est. Priority Date: 10/01/2009
• Status: Active Grant

• Current Assignee: Sun Patent Trust
• Original Assignee: Sun Patent Trust
• Inventors: Ogawa, Yoshihiko, Nishio, Akihiko, Iwai, Takashi, Nakao, Seigo, Imamura, Daichi, Sumasu, Atsushi
• Granted Patent: US 10,057,000 B2
• Time in Patent Office: Days
• CPC Class Codes: H04B 7/0452 Multi-user MIMO systems
• CPC Class Codes: H04B 7/0689 using different transmission schemes, at least one of them being a diversity transmission scheme
• CPC Class Codes: H04J 11/003 at the transmitter transmission to multiple receive units in multiple input multiple output [MIMO] H04B7/0452; transmit antenna weighting H04B7/0615
• CPC Class Codes: H04J 13/0048 Walsh
• CPC Class Codes: H04J 13/18 Allocation of orthogonal codes
• CPC Class Codes: H04L 5/005 of common pilots, i.e. pilots destined for multiple users or terminals
• CPC Class Codes: H04W 72/23 in the downlink direction of a wireless link, i.e. towards a terminal
• CPC Class Codes: H04W 72/54 based on quality criteria
• CPC Class Codes: H04W 88/02 Terminal devices
• CPC Class Codes: H04W 88/08 Access point devices

Abstract

A terminal apparatus is disclosed wherein even in a case of applying SU-MIMO and MU-MIMO at the same time, the inter-sequence interference in a plurality of pilot signals used by the same terminal can be suppressed to a low value, while the inter-sequence interference in pilot signal between terminals can be reduced. In this terminal apparatus: a pilot information deciding unit decides, based on allocation control information, Walsh sequences of the respective ones of first and second stream groups at least one of which includes a plurality of streams; and a pilot signal generating unit forms a transport signal by using the decided Walsh sequences to spread the streams included in the first and second stream groups. During this, Walsh sequences orthogonal to each other are established in the first and second stream groups, and users are allocated on a stream group-by-stream group basis.

Claims

1. An integrated circuit to control a process performed by a terminal apparatus, the process comprising:

generating a reference signal using an orthogonal sequence associated with each of a plurality of layer numbers, the orthogonal sequence being one of a plurality of orthogonal sequences corresponding to a first orthogonal sequence [1, 1] and a second orthogonal sequence [1, −

1]; and

transmitting the reference signal multiplexed with a data signal having a bandwidth that is different from a bandwidth of a data signal transmitted by another terminal apparatus,

wherein the layer numbers correspond to a first layer, a second layer, a third layer and a fourth layer, and

the generating includes generating the reference signal using the orthogonal sequence, which is associated with each of the layer numbers by one of a plurality of associations including;

(i) a first association, in which the first layer and the second layer are associated with the first orthogonal sequence, and the third layer and the fourth layer are associated with the second orthogonal sequence;

(ii) a second association, in which the first layer and the second layer are associated with the second orthogonal sequence, and the third layer and the fourth layer are associated with the first orthogonal sequence;

(iii) a third association, in which all layers including the first layer, the second layer, the third layer and the fourth layer are associated with the first orthogonal sequence; and

(iv) a fourth association, in which all layers including the first layer, the second layer, the third layer and the fourth layer are associated with the second orthogonal sequence.

2. The integrated circuit according to claim 1, comprising:

circuitry which, in operation, controls the process;

at least one input coupled to the circuitry, wherein the at least one input, in operation, inputs data; and

at least one output coupled to the circuity, wherein the at least one output, in operation, outputs data.

3. The integrated circuit according to claim 1, wherein the generating includes generating the reference signal using a cyclic shift value associated with each of the layer numbers.

4. The integrated circuit according to claim 3, wherein the cyclic shift value is one of 12 cyclic shifts values ranging from 0 to 11, and

the generating includes generating the reference signal using the cyclic shift value, which is associated with each of the layer numbers by an association that:

a difference between cyclic shift values, with which the first layer and the second layer are respectively associated, is 6;

a difference between cyclic shift values, with which the third layer and the fourth layer are respectively associated, is 6; and

a difference between cyclic shift values, with which the first layer and the third layer are respectively associated, is 3.

5. An integrated circuit to control a process performed by a terminal apparatus, the method comprising:

generating a reference signal using an orthogonal sequence associated with each of a plurality of layer numbers, the orthogonal sequence being one of a plurality of orthogonal sequences corresponding to a first orthogonal sequence [1, 1] and a second orthogonal sequence [1, −

1]; and

transmitting the reference signal multiplexed with a data signal having a bandwidth that is different from a bandwidth of a data signal transmitted by another terminal apparatus,

wherein the layer numbers are consecutive numbers, and

the generating includes generating the reference signal using the orthogonal sequence, which is associated with each of the layer numbers by one of a plurality of associations including;

(i) a first association, in which the first to a Nw-th layer(s) are associated with the first orthogonal sequence, and a (Nw+1)-th and subsequent layer(s) are associated with the second orthogonal sequence; and

(ii) a second association, in which the first to the Nw-th layer(s) are associated with the second orthogonal sequence, and the (Nw+1)-th and subsequent layer(s) are associated with the first orthogonal sequence,

wherein Nw is a positive integer.

6. The integrated circuit according to claim 5, comprising:

circuitry which, in operation, controls the process;

at least one input coupled to the circuitry, wherein the at least one input, in operation, inputs data; and

at least one output coupled to the circuity, wherein the at least one output, in operation, outputs data.

7. The integrated circuit according to claim 5, wherein the generating includes generating the reference signal using a cyclic shift value associated with each of the layer numbers.

8. The integrated circuit according to claim 7, wherein the cyclic shift value is one of 12 cyclic shifts values ranging from 0 to 11, and

the generating includes generating the reference signal using the cyclic shift value, which is associated with each of the layer numbers by an association that:

a difference between cyclic shift values, with which the first layer and the second layer are respectively associated, is 6;

a difference between cyclic shift values, with which the third layer and the fourth layer are respectively associated, is 6; and

a difference between cyclic shift values, with which the first layer and the third layer are respectively associated, is 3.

9. The integrated circuit according to claim 5, wherein the Nw is variable.

10. The integrated circuit according to claim 5, wherein a number of layers is 4, and the Nw is 2 or 4.

11. The integrated circuit according to claim 5, wherein the layer numbers correspond to the first layer, the second layer, a third layer and a fourth layer, and when the Nw is 2:

in the first association, the first layer and the second layer are associated with the first orthogonal sequence, and the third layer and the fourth layer are associated with the second orthogonal sequence; and

in the second association, the first layer and the second layer are associated with the second orthogonal sequence, and the third layer and the fourth layer are associated with the first orthogonal sequence.

12. The integrated circuit according to claim 5, wherein the layer numbers correspond to the first layer, the second layer, a third layer and a fourth layer, and when the Nw is 4:

in the first association, the first layer, the second layer, the third layer and the fourth layer are associated with the first orthogonal sequence; and

in the second association, the first layer, the second layer, the third layer and the fourth layer are associated with the second orthogonal sequence.

13. An integrated circuit embedded in a terminal apparatus, the integrated circuit comprising circuitry, which, in operation:

generates a reference signal using an orthogonal sequence associated with each of a plurality of layer numbers, the orthogonal sequence being one of a plurality of orthogonal sequences corresponding to a first orthogonal sequence [1, 1] and a second orthogonal sequence [1, −

1]; and

controls transmission of the reference signal multiplexed with a data signal having a bandwidth that is different from a bandwidth of a data signal transmitted by another terminal apparatus,

wherein the layer numbers correspond to a first layer, a second layer, a third layer and a fourth layer, and

the circuitry, in operation, generates the reference signal using the orthogonal sequence, which is associated with each of the layer numbers by one of a plurality of associations including;

(i) a first association, in which the first layer and the second layer are associated with the first orthogonal sequence, and the third layer and the fourth layer are associated with the second orthogonal sequence;

(ii) a second association, in which the first layer and the second layer are associated with the second orthogonal sequence, and the third layer and the fourth layer are associated with the first orthogonal sequence;

(iii) a third association, in which all layers including the first layer, the second layer, the third layer and the fourth layer are associated with the first orthogonal sequence; and

(iv) a fourth association, in which all layers including the first layer, the second layer, the third layer and the fourth layer are associated with the second orthogonal sequence.

14. The integrated circuit according to claim 13, comprising:

at least one input coupled to the circuitry, wherein the at least one input, in operation, inputs data; and

at least one output coupled to the circuity, wherein the at least one output, in operation, outputs data.

15. The integrated circuit according to claim 13, wherein the circuitry, in operation, generates the reference signal using a cyclic shift value associated with each of the layer numbers.

16. The integrated circuit according to claim 15, wherein the cyclic shift value is one of 12 cyclic shifts values ranging from 0 to 11, and

the circuitry, in operation, generates the reference signal using the cyclic shift value, which is associated with each of the layer numbers by an association that:

a difference between cyclic shift values, with which the first layer and the second layer are respectively associated, is 6;

a difference between cyclic shift values, with which the third layer and the fourth layer are respectively associated, is 6; and

a difference between cyclic shift values, with which the first layer and the third layer are respectively associated, is 3.

17. An integrated circuit embedded in a terminal apparatus, the integrated circuit comprising circuitry, which, in operation:

generates a reference signal using an orthogonal sequence associated with each of a plurality of layer numbers, the orthogonal sequence being one of a plurality of orthogonal sequences corresponding to a first orthogonal sequence [1, 1] and a second orthogonal sequence [1, −

1]; and

controls transmission of the reference signal multiplexed with a data signal having a bandwidth that is different from a bandwidth of a data signal transmitted by another terminal apparatus,

wherein the layer numbers are consecutive numbers, and

the circuitry, in operation, generates the reference signal using the orthogonal sequence, which is associated with each of the layer numbers by one of a plurality of associations including;

(i) a first association, in which the first to a Nw-th layer(s) are associated with the first orthogonal sequence, and a (Nw+1)-th and subsequent layer(s) are associated with the second orthogonal sequence; and

(ii) a second association, in which the first to the Nw-th layer(s) are associated with the second orthogonal sequence, and the (Nw+1)-th and subsequent layer(s) are associated with the first orthogonal sequence,

wherein Nw is a positive integer.

18. The integrated circuit according to claim 17, comprising:

at least one input coupled to the circuitry, wherein the at least one input, in operation, inputs data; and

at least one output coupled to the circuity, wherein the at least one output, in operation, outputs data.

19. The integrated circuit according to claim 17, wherein the circuitry, in operation, generates the reference signal using a cyclic shift value associated with each of the layer numbers.

20. The integrated circuit according to claim 19, wherein the cyclic shift value is one of 12 cyclic shifts values ranging from 0 to 11, and

the circuitry, in operation, generates the reference signal using the cyclic shift value, which is associated with each of the layer numbers by an association that:

a difference between cyclic shift values, with which the first layer and the second layer are respectively associated, is 6;

a difference between cyclic shift values, with which the third layer and the fourth layer are respectively associated, is 6; and

a difference between cyclic shift values, with which the first layer and the third layer are respectively associated, is 3.

21. The integrated circuit according to claim 17, wherein the Nw is variable.

22. The integrated circuit according to claim 17, wherein a number of layers is 4, and the Nw is 2 or 4.

23. The integrated circuit according to claim 17, wherein the layer numbers correspond to the first layer, the second layer, a third layer and a fourth layer, and when the Nw is 2:

in the first association, the first layer and the second layer are associated with the first orthogonal sequence, and the third layer and the fourth layer are associated with the second orthogonal sequence; and

in the second association, the first layer and the second layer are associated with the second orthogonal sequence, and the third layer and the fourth layer are associated with the first orthogonal sequence.

24. The integrated circuit according to claim 17, wherein the layer numbers correspond to the first layer, the second layer, a third layer and a fourth layer, and when the Nw is 4:

in the first association, the first layer, the second layer, the third layer and the fourth layer are associated with the first orthogonal sequence; and

in the second association, the first layer, the second layer, the third layer and the fourth layer are associated with the second orthogonal sequence.