CONTROLLING ACCESS TO PREVIOUSLY-STORED LOGIC IN A RECONFIGURABLE LOGIC DEVICE

• US 20180095670A1
• Filed: 09/30/2016
• Published: 04/05/2018
• Est. Priority Date: 09/30/2016
• Status: Active Grant

• Current Assignee: Amazon Technologies, Inc. (Amazon.com, Inc.)
• Original Assignee: Amazon Technologies, Inc. (Amazon.com, Inc.)
• Inventors: Davis, Mark Bradley, Izenberg, Erez, Johnson, Robert Michael, Khan, Asif, Atta, Islam Mohamed Hatem Abdulfattah Mohamed, Bshara, Nafea, Pettey, Christopher Joseph
• Granted Patent: US 10,642,492 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 15/7871 Reconfiguration support, e.g. configuration loading, configuration switching, or hardware OS
• CPC Class Codes: G06F 21/51 at application loading time, e.g. accepting, rejecting, starting or inhibiting executable software based on integrity or source reliability
• CPC Class Codes: G06F 2221/2143 Clearing memory, e.g. to prevent the data from being stolen
• CPC Class Codes: G06F 3/0607 by facilitating the process of upgrading existing storage systems, e.g. for improving compatibility between host and storage device
• CPC Class Codes: G06F 3/0635 by changing the path, e.g. traffic rerouting, path reconfiguration
• CPC Class Codes: G06F 3/0644 Management of space entities, e.g. partitions, extents, pools
• CPC Class Codes: G06F 3/0685 Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories

Abstract

Methods and apparatus are disclosed for securely erasing partitions of reconfigurable logic devices such as FPGAs in a multi-tenant server environment. In one example, a method of securely erasing an FPGA includes identifying one partition of previously-programmed resources in the FPGA, erasing the identified partition by storing new values in memory or storage elements of the identified partition, and storing new values in memory or storage elements of additional external resources electrically connected to the integrated circuit and associated with the identified partition. Thus, other partitions and subsequent users of the identified partition are prevented from accessing the securely erased data. A configuration circuit, accessible by a host computer via DMA, can be programmed into the FPGA reconfigurable logic for performing the disclosed erasing operations.

Claims

1. A system, comprising:

a computing host comprising one or more processors; and

a single field programmable gate array (FPGA) configured into a plurality of logic device portions, the portions comprising;

one or more application logic partitions, each of the application logic partitions comprising;

(1) reconfigurable logic and (2) memory devices coupled to the reconfigurable logic, the memory devices being accessed by operation of the application logic partition'"'"'s respective reconfigurable logic,

a host logic partition, and

an internal configuration circuit configured to erase data stored in a selected one of the application logic partitions.

2. The system of claim 1, wherein:

the data that the internal configuration circuit is configured to erase comprises data stored in one or more of latches, flip-flops, or configuration memory of the selected one of the application logic partitions; and

the internal configuration circuit is further configured to erase data stored in the memory devices, and wherein the memory devices comprise internal RAM of the FPGA.

3. The system of claim 1, wherein the internal configuration circuit is further configured to receive instructions or data via a direct memory access (DMA) that causes the internal configuration circuit to erase the data.

4. The system of claim 1, wherein the internal configuration circuit is further configured to isolate the selected application logic partition prior to erasing by decoupling the selected application logic partition from other partitions.

5. A method comprising:

responsive to receiving a request to erase application data from a reconfigurable hardware platform;

identifying a partition of previously-programmed resources in a reconfigurable logic device;

storing new values in memory or storage elements of the identified partition;

identifying additional resources associated with the identified partition of programmable resources; and

storing new values in memory or storage elements of the additional resources.

6. The method of claim 5, wherein the storing new values in the identified partition comprises configuring clearing logic in the reconfigurable logic device through a configuration port of the reconfigurable logic device to change values in the memory or storage elements.

7. The method of claim 5, wherein the request is generated when terminating an instance comprising the reconfigurable logic host.

8. The method of claim 5, wherein the request is received from a supervisor process executing on a host computer coupled to the reconfigurable logic device.

9. The method of claim 5, wherein the reconfigurable logic device comprises a host partition controlled by a supervisor process executing on a host computer, and wherein performing the storing new values in the identified partition comprises operating a circuit within the host partition to scrub values stored in the identified partition.

10. The method of claim 5, further comprising:

reconfiguring logic of the identified partition to comprise a scrubber circuit, wherein the scrubber circuit performs the storing new values in memory or storage elements of the identified partition or the storing new values in memory or storage elements of the additional resources.

11. The method of claim 5, wherein the identified partition comprises a scrubber circuit coupled to the additional resources, and wherein the method further comprises operating the scrubber circuit to perform the storing the new values in the additional resources.

12. The method of claim 5, wherein the storing new values in the partition comprises storing a known pattern values in the memory or storage elements, the known pattern of values including:

all zero values, all one values, all of a predetermined set of one or more values, or random values.

13. The method of claim 5, wherein the reconfigurable logic device comprises a plurality of partitions including the identified partition, the method further comprising:

continuing operation of circuitry in the other partitions while performing the storing new values in memory or storage elements of the identified partition.

14. The method of claim 5, wherein the additional resources include at least one of the following devices coupled to an integrated circuit comprising the reconfigurable logic devices:

a synchronous dynamic random access memory device (DRAM), a hybrid memory cube (HMC), a co-processor, a network interface comprising network address information, or a pseudorandom number generator.

15. The method of claim 5, wherein:

the method further comprises receiving a clearing bitstream from a logic repository database via the reconfigurable logic host; and

the storing new values in the identified partition comprises applying the clearing bitstream to an internal or external configuration port of the reconfigurable logic device.

16. The method of claim 5, further comprising:

receiving, from a host computer coupled to the reconfigurable logic device, a description of application logic to be programmed into the identified partition;

generating configuration data comprising the application logic and an internal configuration circuit; and

programming the reconfigurable logic device with the configuration data to form a circuit for the application logic and the internal configuration circuit, wherein the internal configuration circuit is configured to perform the storing new values in the identified portion or storing new values in memory or storage elements of the additional resources.

17. The method of claim 5, further comprising:

launching a virtual machine instance coupled to the identified partition of the reconfigurable logic device and the additional resources;

with the identified partition, performing operations specified in instructions received from a user via a computer network; and

terminating the virtual machine instance, the terminating including erasing data by performing the storing new values in the identified portion and the additional resources.

18. The method of claim 5, further comprising:

launching a first virtual machine instance coupled to the identified partition of the reconfigurable logic device and the additional resources;

terminating the first virtual machine instance; and

launching a second virtual machine instance, wherein the second launching comprises erasing the identified partition by delaying the storing of new values in the identified portion and the additional resources until the second launching is initiated.

19. A system, comprising:

a computing host comprising one or more processors;

a reconfigurable logic device coupled to the computing host, the reconfigurable logic device having logic partitioned into a plurality of user logic partitions, each of the user logic partitions being controlled by a different process executing on the computing host; and

a reconfiguration circuit configured to erase data from a selected one of the user logic partitions by overwriting values in memory and storage and clearing logic configurations of the selected user logic partition.

20. The system of claim 19, wherein the reconfiguration circuit is further configured to erase data from additional resources coupled to an integrated circuit comprising the reconfigurable logic devices, the additional resources being associated with the selected user logic partition.

21. The system of claim 19, wherein the reconfiguration circuit is further configured to erase data from the selected logic partition by applying a configuration bitstream to the reconfigurable logic device.

22. The system of claim 19, wherein the reconfiguration circuit is further configured to allow continued operation of partitions within the reconfigurable logic device other than the selected user logic partition while the reconfiguration circuit erases the data.

23. The system of claim 19, wherein the reconfiguration circuit is coupled to the host computer with a direct memory access (DMA) connection, and wherein the host computer is configured to send commands or data via the DMA connection, the commands or data causing the reconfiguration circuit to erase the data.

24. The system of claim 19, wherein:

the memory comprises;

block random access memory (RAM),

static RAM;

dynamic RAM,

flash memory,

embedded DRAM,

configuration memory,

distributed RAM, or

lookup-table RAM; and

the storage comprises;

latches, or

flip-flops.