LOW ENERGY CONSUMPTION MANTISSA MULTIPLICATION FOR FLOATING POINT MULTIPLY-ADD OPERATIONS
First Claim
1. A processor comprising:
- a floating point multiply-add unit having inputs coupled to receive a floating point multiplier data element, a floating point multiplicand data element, and a floating point addend data element, the floating point multiply-add unit including;
a mantissa multiplier to multiply a mantissa of the floating point multiplier data element and a mantissa of the floating point multiplicand data element to calculate a mantissa product, the mantissa multiplier including;
a most significant bit portion to calculate most significant bits of the mantissa product;
a least significant bit portion to calculate least significant bits of the mantissa product, wherein the mantissa multiplier has a plurality of different possible sizes of the least significant bit portion; and
energy consumption reduction logic to selectively reduce energy consumption of the least significant bit portion, but not the most significant bit portion, to cause the least significant bit portion to not calculate the least significant bits of the mantissa product.
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Abstract
A floating point multiply-add unit having inputs coupled to receive a floating point multiplier data element, a floating point multiplicand data element, and a floating point addend data element. The multiply-add unit including a mantissa multiplier to multiply a mantissa of the multiplier data element and a mantissa of the multiplicand data element to calculate a mantissa product. The mantissa multiplier including a most significant bit portion to calculate most significant bits of the mantissa product, and a least significant bit portion to calculate least significant bits of the mantissa product. The mantissa multiplier has a plurality of different possible sizes of the least significant bit portion. Energy consumption reduction logic to selectively reduce energy consumption of the least significant bit portion, but not the most significant bit portion, to cause the least significant bit portion to not calculate the least significant bits of the mantissa product.
39 Citations
25 Claims
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1. A processor comprising:
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a floating point multiply-add unit having inputs coupled to receive a floating point multiplier data element, a floating point multiplicand data element, and a floating point addend data element, the floating point multiply-add unit including; a mantissa multiplier to multiply a mantissa of the floating point multiplier data element and a mantissa of the floating point multiplicand data element to calculate a mantissa product, the mantissa multiplier including; a most significant bit portion to calculate most significant bits of the mantissa product; a least significant bit portion to calculate least significant bits of the mantissa product, wherein the mantissa multiplier has a plurality of different possible sizes of the least significant bit portion; and energy consumption reduction logic to selectively reduce energy consumption of the least significant bit portion, but not the most significant bit portion, to cause the least significant bit portion to not calculate the least significant bits of the mantissa product. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A method in a processor comprising:
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starting a floating point multiply-add operation on a floating point multiplier data element, a floating point multiplicand data element, and a floating point addend data element; and multiplying a mantissa of the floating point multiplier data element and a mantissa of the floating point multiplicand data element to calculate a mantissa product, without calculating a least significant bit portion of the mantissa product that has a size that is based, at least in part, on the floating point addend data element. - View Dependent Claims (16, 17, 18, 19, 20)
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21. A computer system comprising:
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an interconnect; a memory coupled with the interconnect; and a processor coupled with the interconnect, the processor comprising; a floating point multiply-add unit having inputs coupled to receive a floating point multiplier data element, a floating point multiplicand data element, and a floating point addend data element, the floating point multiply-add unit including; a mantissa multiplier to multiply a mantissa of the floating point multiplier data element and a mantissa of the floating point multiplicand data element to calculate a mantissa product, the mantissa multiplier including; a most significant bit portion to calculate most significant bits of the mantissa product; a least significant bit portion to calculate least significant bits of the mantissa product, wherein the mantissa multiplier has a plurality of different possible sizes of the least significant bit portion; and energy consumption reduction logic to selectively reduce energy consumption of the least significant bit portion, but not the most significant bit portion, to cause the least significant bit portion to not calculate the least significant bits of the mantissa product. - View Dependent Claims (22, 23, 24, 25)
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Specification