Field-Programmable Crossbar Array For Reconfigurable Computing

• US 20180095930A1
• Filed: 10/03/2017
• Published: 04/05/2018
• Est. Priority Date: 10/03/2016
• Status: Active Grant

• Current Assignee: Board of Regents of the University of Michigan (University of Michigan)
• Original Assignee: Board of Regents of the University of Michigan (University of Michigan)
• Inventors: LU, Wei, ZIDAN, Mohammed A.
• Granted Patent: US 10,346,347 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 2213/70 Resistive array aspects
• CPC Class Codes: G11C 2213/77 Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: H03K 19/177 arranged in matrix form
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

For decades, advances in electronics were directly related to the scaling of CMOS transistors according to Moore'"'"'s law. However, both the CMOS scaling and the classical computer architecture are approaching fundamental and practical limits. A novel memory-centric, reconfigurable, general purpose computing platform is proposed to handle the explosive amount of data in a fast and energy-efficient manner. The proposed computing architecture is based on a single physical resistive memory-centric fabric that can be optimally reconfigured and utilized to perform different computing and data storage tasks in a massively parallel approach. The system can be tailored to achieve maximal energy efficiency based on the data flow by dynamically allocating the basic computing fabric to storage, arithmetic, and analog computing including neuromorphic computing tasks.

Claims

1. A field-programmable crossbar array for reconfigurable computing, comprising:

a plurality of crossbar modules interconnected together, each crossbar module is comprised of at least one interface circuit and an array of resistive memory devices arranged in columns and rows, such that resistive memory devices in each row of the array are interconnected by a respective bitline and resistive memory devices in each column of the array are interconnected by a respective wordline;

wherein each resistive memory device in the array of resistive memory devices has an associated threshold voltage and is configured to store a data value therein as a resistance value;

wherein the at least one interface circuit is electrically connected to each bitline in the array of resistive memory devices and is electrically connected to each wordline in the array of resistive memory devices, wherein the at least one interface circuit cooperatively operates with the array of resistive memory devices to perform an arithmetic operation on data values stored in the array of resistive memory devices.

2. The field-programmable crossbar array of claim 1 wherein each resistive memory device in the array of resistive memory devices is configured to exhibit a high resistive state and a low resistive state, where the high resistive state represents a zero and the low resistive state represents a one.

3. The field-programmable crossbar array of claim 2 wherein the at least one interface circuit performs an addition operation by applying a voltage to each bitline in the array of resistive memory devices and measures output current on one or more of the wordlines in the array of resistive memory devices, such that magnitude of the output current on a given wordline indicates a number of ones stored by the resistive memory devices in the respective column.

4. The field-programmable crossbar array of claim 3 wherein the voltage applied for the addition operation is lower than the threshold voltage of the resistive memory devices.

5. The field-programmable crossbar array of claim 3 wherein the at least one interface circuit performs vector-matrix multiplication by collecting the currents from multiple columns in the array of resistive memory devices.

6. The field-programmable crossbar array of claim 3 wherein the at least one interface circuit performs vector multiplication by collecting current of one or more selected columns in the array of resistive memory devices.

7. The field-programmable crossbar array of claim 2 wherein the at least one interface circuit is configured to copy data values in a given crossbar module between rows or columns of the array of resistive memory devices in the given crossbar module.

8. The field-programmable crossbar array of claim 7 wherein the at least one interface circuit copies data values between rows of the array of resistive memory devices by resetting resistive memory devices in a destination row to a high resistive state and subsequently applying a write voltage between the bitline of the destination row and the bitline of the source row, where the write voltage is greater than the threshold voltage of the resistive memory devices.

9. The field-programmable crossbar array of claim 7 wherein the at least one interface circuit copies data values between rows of the array of resistive memory devices further comprises applying a bias voltage to select wordlines in the array of resistive memory devices while applying a write voltage between the bitline of the destination row and the bitline of a source row, such that data values in columns corresponding to the selected wordlines are not copied from the source row to the destination row

10. The field-programmable crossbar array of claim 2 wherein the at least one interface circuit performs neuromorphic computing through vector multiplication between an input vector and a weight vector, where n columns in a given array of resistive devices store n bit weights therein.

11. A field-programmable crossbar array for reconfigurable computing, comprising:

a plurality of crossbar modules interconnected together, each crossbar module is comprised of at least one interface circuit and an array of resistive memory devices arranged in columns and rows, such that resistive memory devices in each row of the array are interconnected by a respective bitline and resistive memory devices in each column of the array are interconnected by a respective wordline;

wherein each resistive memory device in the array of resistive memory devices has an associated threshold voltage and is configured to store a data value therein as a resistance value;

wherein the at least one interface circuit is electrically connected to each bitline in the array of resistive memory devices and is electrically connected to each wordline in the array of resistive memory devices, wherein the at least one interface circuit is configured to copy data values in a given crossbar module between rows or columns of the array of resistive memory devices in the given crossbar module and the at least one interface circuit cooperatively operates with the array of resistive memory devices to perform an arithmetic operation on data values stored in the array of resistive memory devices.

12. The field-programmable crossbar array of claim 11 wherein each resistive memory device in the array of resistive memory devices is configured to exhibit a high resistive state and a low resistive state, where the high resistive state represents a zero and the low resistive state represents a one.

13. The field-programmable crossbar array of claim 12 wherein the at least one interface circuit performs an addition operation by applying a voltage to each bitline in the array of resistive memory devices and measures output current on one or more of the wordlines in the array of resistive memory devices, such that magnitude of the output current on a given wordline indicates a number of ones stored by the resistive memory devices in the respective column.

14. The field-programmable crossbar array of claim 11 wherein the at least one interface circuit copies data values between rows of the array of resistive memory devices by resetting resistive memory devices in a destination row to a high resistive state and subsequently applying a write voltage between the bitline of the destination row and the bitline of the source row, where the write voltage is greater than the threshold voltage of the resistive memory devices.

15. The field-programmable crossbar array of claim 11 wherein the at least one interface circuit copies data values between rows of the array of resistive memory devices further comprises applying a bias voltage to select wordlines in the array of resistive memory devices while applying a write voltage between the bitline of the destination row and the bitline of a source row, such that data values in columns corresponding to the selected wordlines are not copied from the source row to the destination row

16. A field-programmable crossbar array for reconfigurable computing, comprising:

a plurality of crossbar modules interconnected together, each crossbar module is comprised of at least one interface circuit and an array of resistive memory devices arranged in columns and rows, such that resistive memory devices in each row of the array are interconnected by a respective bitline and resistive memory devices in each column of the array are interconnected by a respective wordline;

wherein each resistive memory device in the array of resistive memory devices has an associated threshold voltage and is configured to store a data value therein as a resistance value;

wherein the at least one interface circuit is electrically connected to each bitline in the array of resistive memory devices and is electrically connected to each wordline in the array of resistive memory devices, wherein the at least one interface circuit cooperatively operates with the array of resistive memory devices to perform an arithmetic operation on data values stored in the array of resistive memory devices and to perform neuromorphic computing in the array of resistive memory devices.

17. The field-programmable crossbar array of claim 16 the at least one interface circuit performs neuromorphic computing through vector multiplication between an input vector and a weight vector, where n columns in a given array of resistive devices store n bit weights therein. 18, The field-programmable crossbar array of claim 16 wherein each resistive memory device in the array of resistive memory devices is configured to exhibit a high resistive state and a low resistive state, where the high resistive state represents a zero and the low resistive state represents a one.

19. The field-programmable crossbar array of claim 18 wherein the at least one interface circuit performs an addition operation by applying a voltage to each bitline in the array of resistive memory devices and measures output current on one or more of the wordlines in the array of resistive memory devices, such that magnitude of the output current on a given wordline indicates a number of ones stored by the resistive memory devices in the respective column.