FACILITATION OF SPIN-COAT PLANARIZATION OVER FEATURE TOPOGRAPHY DURING SUBSTRATE FABRICATION

• US 20180096905A1
• Filed: 10/04/2017
• Published: 04/05/2018
• Est. Priority Date: 10/04/2016
• Status: Active Grant

• Current Assignee: Tokyo Electron Limited
• Original Assignee: Tokyo Electron Limited
• Inventors: Burns, Ryan L., Rathsack, Benjamen M., Somervell, Mark H., Muramatsu, Makoto
• Granted Patent: US 10,622,267 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 30/20 Design optimisation, verification or simulation optimisation, verification or simulation of circuit designs G06F30/30
• CPC Class Codes: H01L 21/02282 liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
• CPC Class Codes: H01L 21/31055 the removal being a chemical etching step, e.g. dry etching etching per se H01L21/311
• CPC Class Codes: H01L 22/12 for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions electrical measurement of diffusions H01L22/14
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps

Abstract

Described herein are technologies to facilitate device fabrication, especially those that involve spin-on coatings of a substrate (e.g., wafer). More particularly, technologies described herein facilitate the planarization (i.e., flatness) of spin-on coatings during the device fabrication to form a uniformly planar film or layer on the substrate. This abstract itself is not intended to limit the scope of this patent. The scope of the present invention is pointed out in the appending claims.

Claims

1. A method of facilitating spin-coat planarization over feature topography during substrate fabrication, the method comprising:

generating a topography map of features of a patterned substrate, the generating the topography map is based, at least in part, on a substrate patterning information;

generating a film-thickness model of a substrate after a spin-on coating is applied to the patterned substrate, wherein the model generation is based, at least in part, on the topography map and on a thickness of a film being deposited on the patterned substrate;

determining film thickness of an area of the film-thickness model falls with a defined range;

based upon that determining, declaring that area of the film-thickness model to be planar;

otherwise, generating suggested remedies to enhance planarization of that area of the film-thickness model, wherein the remedies affect the substrate fabrication.

2. A method of claim 1 further comprising:

selecting one or more selected remedies;

performing the one or more selected remedies.

3. A method of facilitating spin-coat planarization over feature topography during substrate fabrication, the method comprising:

receiving substrate patterning information for a semiconductor substrate;

generating a topography map of a patterned substrate based, at least in part, on the substrate patterning information;

receiving data regarding a plurality film thickness points associated with a film deposited on the semiconductor substrate; and

generating a model of film thickness for the semiconductor substrate based, at least in part, on the data of the plurality of film thickness points.

4. A method of claim 3, wherein the substrate patterning information comprises feature dimensions, mask tone, or film thickness measurement values.

5. A method of claim 3, wherein the topography map comprises features varying by height, width, and distance between the features.

6. A method of claim 3, wherein the model of film thickness comprises an estimated film thickness based, at least in part, on a blanket film thickness, a localized pattern height, a localized pattern width, and surrounding density of features within the patterned substrate.

7. A method of claim 3, wherein the plurality of film thickness data comprises thickness data of one or more films on the semiconductor substrate.

8. A method of claim 3, wherein the film comprises a blanket film, a patterned film, or a treated film.

9. A method comprising:

receiving substrate patterning information for a patterned substrate;

receiving a film thickness model based, at least in part, on a thickness of a film being deposited on the patterned substrate and an arrangement of features on the patterned substrate; and

generating a deposited film thickness model of the patterned substrate based, at least in part, on the substrate patterning information and the film thickness model.

10. A method of claim 9, wherein the film thickness model is based, at least in part, on a blanket film thickness and topography of the patterned substrate.

11. A method of claim 9, wherein the generating of the deposited film thickness model comprises:

assigning grid points across the patterned substrate;

determining a trench depth at or around the grid points on the substrate;

determining a calculation distance from the grid points;

calculating a film thickness for the grid points based, at least in part, on a blanket film thickness, the trench depth proximate to the grid point, a surface area around the grid points, and values from adjacent grid points within the calculation distance of one or more of the grid points.

12. A method of claim 9, wherein the arrangement of features is based, at least in part, on one or more of the following:

feature depth, feature width, or feature surface area at different locations across the patterned substrate.

13. A method of claim 9 further comprising:

comparing the deposited film thickness model to a predetermined specification; and

adjusting one or more process conditions based, at least in part, on the comparing of the deposited film thickness model and the predetermined specification.

14. A method of claim 9 further comprising:

comparing the deposited film thickness model to a predetermined specification; and

adjusting one or more process conditions based, at least in part, on the comparing of the deposited film thickness model and the predetermined specification,

wherein the one or more process conditions include one or more of following;

spin speed for a film being deposited on a substrate, focus or dose of a lithography process used to pattern the substrate, etch time, or etch power.

15. A method of claim 9 further comprising:

comparing the deposited film thickness model to a predetermined specification;

adjusting one or more process targets based, at least in part, on the comparing of the process simulations with the predetermined specification.

16. A method of claim 9 further comprising:

comparing the deposited film thickness model to a predetermined specification; and

adjusting one or more process targets based, at least in part, on the comparing of the process simulations with the predetermined value,

wherein the one or more process targets include one or more of the following;

deposition thickness, trench depth, film non-uniformity.

17. A method of claim 9 further comprising:

comparing the deposited film thickness model to a predetermined specification; and

adjusting one or more design conditions based, at least in part, on the comparing of the deposited film thickness model and the predetermined specification.

18. A method of claim 9 further comprising:

comparing the deposited film thickness model to a predetermined specification;

adjusting one or more design conditions based, at least in part, on the comparing of the deposited film thickness model and the predetermined specification,

wherein the design conditions include one or more of following;

device layout, dummy fill layout, mask layout, or other conditions that impact pattern density on the patterned substrate.

19. A method of claim 9, wherein the firm thickness model includes thickness data of one or more films on the semiconductor substrate.

20. A method of claim 9, wherein the film comprises a blanket film, a patterned film, or a treated film.