SEMICONDUCTOR DEVICES WITH ALIGNMENT KEYS
First Claim
1. A semiconductor device, comprising:
- an alignment key on a substrate,wherein the alignment key comprises;
a first sub-alignment key pattern that includes a first conductive pattern, a second conductive pattern, and a capping dielectric pattern that are sequentially stacked on the substrate;
an alignment key trench that penetrates at least a portion of the first sub-alignment key pattern; and
a lower conductive pattern in the alignment key trench,wherein the alignment key trench comprises;
an upper trench that is provided in the capping dielectric pattern that has a first width; and
a lower trench that extends downward from the upper trench that has a second width less than the first width,wherein the lower conductive pattern includes sidewall conductive patterns that are separately disposed on opposite sidewalls of the lower trench.
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Accused Products
Abstract
A semiconductor device includes an alignment key on a substrate. The alignment key includes a first sub-alignment key pattern with a first conductive pattern, a second conductive pattern, and a capping dielectric pattern that are sequentially stacked on the substrate, an alignment key trench that penetrates at least a portion of the first sub-alignment key pattern, and a lower conductive pattern in the alignment key trench. The alignment key trench includes an upper trench that is provided in the capping dielectric pattern that has a first width, and a lower trench that extends downward from the upper trench and that has a second width less than the first width. The lower conductive pattern includes sidewall conductive patterns that are separately disposed on opposite sidewalls of the lower trench.
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Citations
20 Claims
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1. A semiconductor device, comprising:
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an alignment key on a substrate, wherein the alignment key comprises; a first sub-alignment key pattern that includes a first conductive pattern, a second conductive pattern, and a capping dielectric pattern that are sequentially stacked on the substrate; an alignment key trench that penetrates at least a portion of the first sub-alignment key pattern; and a lower conductive pattern in the alignment key trench, wherein the alignment key trench comprises; an upper trench that is provided in the capping dielectric pattern that has a first width; and a lower trench that extends downward from the upper trench that has a second width less than the first width, wherein the lower conductive pattern includes sidewall conductive patterns that are separately disposed on opposite sidewalls of the lower trench. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A semiconductor device, comprising:
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a substrate that includes a chip zone and a scribe lane zone; a gate line in the chip zone; and an alignment key in the scribe lane zone, wherein the gate line comprises a gate dielectric pattern, a lower gate pattern, an upper gate pattern, and a gate capping pattern that are sequentially stacked on the substrate, wherein the alignment key comprises; a first sub-alignment key pattern that includes a buffer dielectric pattern, a first conductive pattern, a second conductive pattern, and a capping dielectric pattern that are sequentially stacked on the substrate; an alignment key trench that penetrates at least a portion of the first sub-alignment key pattern, the alignment key trench including an upper trench that vertically penetrates a portion of the capping dielectric pattern and has a first width and a lower trench that extends downward from the upper trench and has a second width less than the first width; and sidewall conductive patterns that are separately disposed on opposite sidewalls of the lower trench, the buffer dielectric pattern, the first conductive pattern, the second conductive pattern, and the capping dielectric pattern comprising the same materials, respectively, as the gate dielectric pattern, the lower gate pattern, the upper gate pattern, and the gate capping pattern.
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16. A method of fabricating a semiconductor device, comprising the steps of:
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providing a substrate that includes a first region and a second region; sequentially forming a first dielectric layer, a lower conductive layer, an upper conductive layer, and a second dielectric layer on the substrate; forming a first mask pattern on the substrate that covers a portion of the second dielectric layer in the first region and completely covers the second dielectric layer in the second region; etching the substrate using the first mask pattern as an etching mask wherein a gate line is formed in the first region of the substrate, wherein the gate line includes a gate dielectric pattern, a lower gate pattern, an upper gate pattern, and a gate capping pattern that are respectively formed by patterning the first dielectric layer, the lower conductive layer, the upper conductive layer, and the second dielectric layer in the first region; removing the first mask pattern; forming source/drain regions in the substrate on opposite sides of the gate line; forming a lower interlayer dielectric layer on the first region of the substrate; forming a second mask pattern on the substrate that has first openings on the first region that overlap the source/drain regions and a trench-shaped second opening on the second region; etching portions of the lower interlayer dielectric layer exposed through the first openings using the second mask pattern to form lower contact holes that penetrate the lower interlayer dielectric layer and expose the source/drain regions, wherein the second dielectric layer and the upper conductive layer of the second region are sequentially etched to form a preliminary alignment key trench that exposes the lower conductive layer; and removing the second mask pattern. - View Dependent Claims (17, 18, 19, 20)
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Specification