SEMICONDUCTOR DEVICES WITH ALIGNMENT KEYS

• US 20180096947A1
• Filed: 05/30/2017
• Published: 04/05/2018
• Est. Priority Date: 09/30/2016
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Original Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Inventors: LEE, KISEOK, Shin, Sooho, Lee, Juik, Lee, Jun Ho, Kim, Kwangmin, Moon, Ilyoung, Park, Jemin, Seo, Bumseok, Yoon, Chan-Sic, Lee, Hoin
• Granted Patent: US 10,026,694 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 2223/5442 comprising non digital, non alphanumeric information, e.g. symbols
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2223/5446 Located in scribe lines
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/315 with the capacitor higher than a bit line
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate
• CPC Class Codes: H10B 12/482 Bit lines
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures

Abstract

A semiconductor device includes an alignment key on a substrate. The alignment key includes a first sub-alignment key pattern with a first conductive pattern, a second conductive pattern, and a capping dielectric pattern that are sequentially stacked on the substrate, an alignment key trench that penetrates at least a portion of the first sub-alignment key pattern, and a lower conductive pattern in the alignment key trench. The alignment key trench includes an upper trench that is provided in the capping dielectric pattern that has a first width, and a lower trench that extends downward from the upper trench and that has a second width less than the first width. The lower conductive pattern includes sidewall conductive patterns that are separately disposed on opposite sidewalls of the lower trench.

Claims

1. A semiconductor device, comprising:

an alignment key on a substrate,

wherein the alignment key comprises;

a first sub-alignment key pattern that includes a first conductive pattern, a second conductive pattern, and a capping dielectric pattern that are sequentially stacked on the substrate;

an alignment key trench that penetrates at least a portion of the first sub-alignment key pattern; and

a lower conductive pattern in the alignment key trench,

wherein the alignment key trench comprises;

an upper trench that is provided in the capping dielectric pattern that has a first width; and

a lower trench that extends downward from the upper trench that has a second width less than the first width,

wherein the lower conductive pattern includes sidewall conductive patterns that are separately disposed on opposite sidewalls of the lower trench.

2. The semiconductor device of claim 1, wherein the lower trench penetrates the second conductive pattern and exposes the first conductive pattern.

3. The semiconductor device of claim 2, wherein the lower conductive pattern further comprises an interconnect conductive pattern that connects bottom ends of the sidewall conductive patterns.

wherein the interconnect conductive pattern is in contact with the first conductive pattern exposed through the lower trench.

4. The semiconductor device of claim 1, wherein the lower trench penetrates the second conductive pattern and the first conductive pattern and exposes the substrate.

5. The semiconductor device of claim 4, wherein the lower conductive pattern further comprises an interconnect conductive pattern that connects bottom ends of the sidewall conductive patterns,

wherein the interconnect conductive pattern is in contact with the substrate exposed through the lower trench.

6. The semiconductor device of claim 1, wherein the alignment key further comprises an upper conductive pattern on the capping dielectric pattern,

wherein the upper conductive pattern has inner sidewalls aligned with sidewalls of the capping dielectric pattern, wherein the sidewalls of the capping dielectric pattern are exposed through the upper trench.

7. The semiconductor device of claim 1, wherein the upper trench has a depth that is less than a thickness of the capping dielectric pattern.

8. The semiconductor device of claim 1, wherein the first sub-alignment key pattern comprises dielectric spacers, each of which is interposed between one of the opposite sidewalls of the lower trench and one of the sidewall conductive patterns.

9. The semiconductor device of claim 1, further comprising a buried dielectric pattern in the substrate below the first sub-alignment key pattern,

wherein the lower trench penetrates the second and first conductive patterns and extends into the buried dielectric pattern.

10. The semiconductor device of claim 1,

wherein the substrate comprises a first region and a second region around the first region, the alignment key being disposed in the second region, and

wherein the semiconductor device further comprises a gate line that includes a gate dielectric pattern, a lower gate pattern, an upper gate pattern, and a gate capping pattern that are sequentially stacked on the first region.

11. The semiconductor device of claim 10, wherein the first conductive pattern, the second conductive pattern, and the capping dielectric pattern comprises the same materials, respectively, as the lower gate pattern, the upper gate pattern, and the gate capping pattern.

12. The semiconductor device of claim 10, further comprising:

a source/drain region that is provided in the substrate on either side of the gate line in the first region; and

a lower contact plug that is connected to the source/drain region,

wherein the lower conductive pattern includes the same material as the lower contact plug.

13. The semiconductor device of claim 10, wherein the first sub-alignment key pattern comprises a buffer dielectric pattern between the first conductive pattern and the substrate of the second region,

wherein the buffer dielectric pattern includes the same material as the gate dielectric pattern.

14. The semiconductor device of claim 10,

wherein the first region comprises a cell region and a peripheral circuit region, the gate line being disposed in the peripheral circuit region, and

wherein the semiconductor device further comprises a cell conductive line that includes a first cell conductive line, a second cell conductive line, and a cell capping line that are sequentially stacked in the cell region,

the first conductive pattern, the second conductive pattern, and the capping dielectric pattern comprising the same materials, respectively, as the first cell conductive line, the second cell conductive line, and the cell capping line.

15. A semiconductor device, comprising:

a substrate that includes a chip zone and a scribe lane zone;

a gate line in the chip zone; and

an alignment key in the scribe lane zone,

wherein the gate line comprises a gate dielectric pattern, a lower gate pattern, an upper gate pattern, and a gate capping pattern that are sequentially stacked on the substrate,

wherein the alignment key comprises;

a first sub-alignment key pattern that includes a buffer dielectric pattern, a first conductive pattern, a second conductive pattern, and a capping dielectric pattern that are sequentially stacked on the substrate;

an alignment key trench that penetrates at least a portion of the first sub-alignment key pattern, the alignment key trench including an upper trench that vertically penetrates a portion of the capping dielectric pattern and has a first width and a lower trench that extends downward from the upper trench and has a second width less than the first width; and

sidewall conductive patterns that are separately disposed on opposite sidewalls of the lower trench,

the buffer dielectric pattern, the first conductive pattern, the second conductive pattern, and the capping dielectric pattern comprising the same materials, respectively, as the gate dielectric pattern, the lower gate pattern, the upper gate pattern, and the gate capping pattern.

16. A method of fabricating a semiconductor device, comprising the steps of:

providing a substrate that includes a first region and a second region;

sequentially forming a first dielectric layer, a lower conductive layer, an upper conductive layer, and a second dielectric layer on the substrate;

forming a first mask pattern on the substrate that covers a portion of the second dielectric layer in the first region and completely covers the second dielectric layer in the second region;

etching the substrate using the first mask pattern as an etching mask wherein a gate line is formed in the first region of the substrate, wherein the gate line includes a gate dielectric pattern, a lower gate pattern, an upper gate pattern, and a gate capping pattern that are respectively formed by patterning the first dielectric layer, the lower conductive layer, the upper conductive layer, and the second dielectric layer in the first region;

removing the first mask pattern;

forming source/drain regions in the substrate on opposite sides of the gate line;

forming a lower interlayer dielectric layer on the first region of the substrate;

forming a second mask pattern on the substrate that has first openings on the first region that overlap the source/drain regions and a trench-shaped second opening on the second region;

etching portions of the lower interlayer dielectric layer exposed through the first openings using the second mask pattern to form lower contact holes that penetrate the lower interlayer dielectric layer and expose the source/drain regions, wherein the second dielectric layer and the upper conductive layer of the second region are sequentially etched to form a preliminary alignment key trench that exposes the lower conductive layer; and

removing the second mask pattern.

17. The method of claim 16, wherein the first mask pattern in the second region includes a fifth opening through which the second dielectric layer is exposed,

wherein etching the substrate the first mask pattern as an etching mask forms the preliminary alignment key trench in the second region of the substrate that penetrates the second dielectric layer, the upper conductive layer, the lower conductive layer, and the second dielectric layer, to expose a top surface of the substrate

18. The method of claim 16, wherein the first mask pattern protects the first dielectric layer, the lower conductive layer, the upper conductive layer, and the second dielectric layer of the second region when etching the substrate with the first mask pattern.

19. The method of claim 16, wherein the method further comprises:

forming a lower interconnect line layer in the substrate, wherein the lower interconnect line layer of the first region completely fills the lower contact holes and covers the top surface of the lower interlayer dielectric layer, and the lower interconnect line layer of the second region partially fills the preliminary alignment key trench and covers a top surface of the second dielectric layer;

sequentially forming an organic mask layer and a hardmask layer on the substrate, wherein the organic mask layer is formed of a material having an etch selectivity with respect to the hardmask layer, wherein on the first region, the organic mask layer and the hardmask layer cover the lower interconnect line layer, and on the second region, the organic mask layer covers the lower interconnect line layer and fills the preliminary alignment key trench; and

forming a third mask pattern on the hardmask layer that has a third opening on the first region and a fourth opening on the second region that extends along the preliminary alignment key trench.

20. The method of claim 19, further comprising sequentially etching the hardmask layer, the organic mask layer, and the lower interconnect line layer using the third mask pattern as a pattern mask to form a lower interconnect line in the first region from the lower interconnect line layer, wherein the lower interconnect line layer that remains in the lower contact holes forms lower contact plugs, and the lower interconnect line layer of the second region is patterned to form an upper conductive pattern and a lower conductive pattern, wherein the second dielectric layer of the second region is partially etched to form an upper trench in the second dielectric layer of the second region, wherein a remaining portion of the preliminary alignment key trench below the upper trench forms a lower trench, and wherein the third mask pattern and the hardmask layer are completely removed;

and

removing the organic mask layer.