TRANSISTOR WITH IMPROVED AIR SPACER

• US 20180097059A1
• Filed: 10/05/2016
• Published: 04/05/2018
• Est. Priority Date: 10/05/2016
• Status: Active Grant

• Current Assignee: Tessera, Inc. (Adeia Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: BI, Zhenxing, CHENG, Kangguo, LI, Juntao, XU, Peng
• Granted Patent: US 9,941,352 B1
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/283 Deposition of conductive or insulating materials for electrodes conducting electric current
• CPC Class Codes: H01L 21/764 Air gaps H01L21/76264 takes precedence
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 2221/1063 Sacrificial or temporary thin dielectric films in openings in a dielectric
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/4991 comprising an air gap
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

A semiconductor structure and a method for fabricating the same. The semiconductor structure includes a gate stack disposed on a substrate. A gate contact is disposed in contact with an end portion of the gate stack. An air gap spacer is disposed in contact with a portion of the gate stack. The end portion of the gate stack is absent the air gap spacer. The method includes forming a gate contact in contact with a gate stack. A spacer surrounding at least a portion of the gate stack is removed after the gate contact has been formed. The removal of the spacer forms a trench surrounding the gate stack and stopping at the gate contact. An air gap spacer is formed within the trench.

Claims

1. A method for fabricating a semiconductor structure, the method comprising:

forming a gate contact in contact with a gate stack;

after forming the gate contact, removing a spacer surrounding at least a portion of the gate stack, wherein the removing forms a trench surrounding the gate stack and stopping at the gate contact; and

depositing an insulating material within the trench to form an air gap spacer within the trench comprising at least three separate air gaps surrounded by the insulating material on corresponding sides of the gate stack.

2. The method of claim 1, wherein forming the gate contact comprises:

forming the gate contact in contact with a portion of a top surface of a gate of the gate stack, and wrapping the gate contact around a portion of the gate and a portion of an underlying dielectric layer of the gate stack.

3. The method of claim 1, wherein forming the gate contact comprises:

removing a portion of the spacer in contact with an end portion of the gate stack, wherein the removing exposes an end portion of a gate of the gate stack and an underlying dielectric layer, and further exposes sidewalls of the gate and underlying dielectric layer.

4. The method of claim 3, wherein forming the gate contact further comprises:

removing a portion of a cap layer formed on the gate, the etching exposing a top surface of a gate at the end portion of the gate stack;

removing a portion of an insulating layer adjacent to the gate stack; and

forming the gate contact in contact with at least the top surface of the gate, the exposed sidewalls of the gate, and the exposed sidewalls of the underlying dielectric layer.

5. The method of claim 1, further comprising:

prior to forming the gate contact,

forming a source contact in contact with a portion of a source region of a substrate and a sidewall of the spacer; and

forming a drain contact in contact with a portion of a drain region of the substrate and a sidewall of the spacer.

6. The method of claim 5, wherein forming the source contact and the drain contact comprises:

depositing a dielectric material in contact with the source region, drain region, and spacer;

forming a first contact trench adjacent to the spacer, the first contact trench exposing the portion of the source region;

forming a second contact trench adjacent to the spacer, the second contact trench exposing the portion of the drain region; and

filling the first contact trench and the second contact trench with a contact material.

removing a portion of the first spacer at one end of the gate stack.

7. The method of claim 1, wherein forming the air gap spacer comprises:

non-conformally depositing the insulating material within the trench, wherein the non-conformal deposition deposits a greater amount of the insulating material at a top portion of the trench than at a bottom portion of the trench, and wherein the non-conformal deposition forms an air gap between a top portion of the air gap spacer and a bottom portion of the air gap spacer.

21. The method of claim 1, further comprising forming the gate stack, wherein forming the gate stack comprises:

forming a replacement gate structure on a substrate; and

forming the spacer in contact with the replacement gate structure.

22. The method of claim 21, further comprising:

after forming the spacer, forming a source region and a drain region within the substrate.

23. The method of claim 21, further comprising:

after the spacer has been formed, selectively removing the replacement gate stack, wherein the selective removal exposes an active area within the substrate and sidewalls of the spacer;

forming a dielectric layer on and in contact with the active area; and

forming a conductive gate on and in contact with the dielectric layer.

8-20. -20. (canceled)

24. A method for fabricating a semiconductor structure, the method comprising:

forming a plurality of gate contacts, wherein each gate contact of the plurality of gate contacts is in contact with a gate stack of a plurality of gate stacks;

after forming the plurality of gate contacts and for each gate stack of the plurality of gate stacks, removing a spacer surrounding at least a portion of the gate stack, wherein the removing forms a trench surrounding the gate stack and stopping at the gate contact; and

depositing, for each gate stack of the plurality of gate stacks, an insulating material within the trench to form an air gap spacer within each trench comprising at least three separate air gaps surrounded by the insulating material on corresponding sides of the gate stack.

25. The method of claim 24, wherein forming each gate contact of the plurality of gate contact comprises:

forming the gate contact in contact with a portion of a top surface of a gate of the gate stack, and wrapping the gate contact around a portion of the gate and a portion of an underlying dielectric layer of the gate stack.

26. The method of claim 24, wherein forming each gate contact of the plurality of gate contact comprises:

removing a portion of the spacer in contact with an end portion of the gate stack, wherein the removing exposes an end portion of a gate of the gate stack and an underlying dielectric layer, and further exposes sidewalls of the gate and underlying dielectric layer.

27. The method of claim 26, wherein forming each gate contact of the plurality of gate contact further comprises:

removing a portion of a cap layer formed on the gate, the etching exposing a top surface of a gate at the end portion of the gate stack;

removing a portion of an insulating layer adjacent to the gate stack; and

forming the gate contact in contact with at least the top surface of the gate, the exposed sidewalls of the gate, and the exposed sidewalls of the underlying dielectric layer.

28. The method of claim 24, further comprising:

prior to forming each gate contact of the plurality of gate contacts,

forming a plurality of source contacts, wherein each source contact is in contact with a portion of a source region of a substrate and a sidewall of one of the spacers; and

forming a plurality drain contacts, wherein each drain contact in contact with a portion of a drain region of the substrate and a sidewall of one of the spacers.

29. The method of claim 28, wherein forming each source contact of the plurality of source contacts and each drain contact of the plurality of drain contacts comprises:

depositing a dielectric material in contact with the source region, drain region, and spacer;

forming a first contact trench adjacent to the spacer, the first contact trench exposing the portion of the source region;

forming a second contact trench adjacent to the spacer, the second contact trench exposing the portion of the drain region; and

filling the first contact trench and the second contact trench with a contact material.

removing a portion of the first spacer at one end of the gate stack.

30. The method of claim 24, wherein forming the air gap spacer comprises:

non-conformally depositing the insulating material within the trench, wherein the non-conformal deposition deposits a greater amount of the insulating material at a top portion of the trench than at a bottom portion of the trench, and wherein the non-conformal deposition forms an air gap between a top portion of the air gap spacer and a bottom portion of the air gap spacer.

31. The method of claim 24, further comprising forming the plurality of gate stacks, wherein forming each gate stack in the plurality of gate stacks comprises:

forming a replacement gate structure on a substrate; and

forming the spacer in contact with the replacement gate structure.

32. The method of claim 31, further comprising:

after forming the spacer, forming a source region and a drain region within the substrate.

33. The method of claim 31, further comprising:

after the spacer has been formed, selectively removing the replacement gate stack, wherein the selective removal exposes an active area within the substrate and sidewalls of the spacer;

forming a dielectric layer on and in contact with the active area; and

forming a conductive gate on and in contact with the dielectric layer.