SOLID-STATE IMAGING DEVICE AND ELECTRONIC DEVICE

• US 20180098005A1
• Filed: 03/18/2016
• Published: 04/05/2018
• Est. Priority Date: 04/03/2015
• Status: Active Grant

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: HANZAWA, KATSUHIKO
• Granted Patent: US 10,171,761 B2
• Time in Patent Office: Days
• CPC Class Codes: H04N 25/62 Detection or reduction of noise due to excess charges produced by the exposure, e.g. smear, blooming, ghost image, crosstalk or leakage between pixels
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors
• CPC Class Codes: H04N 25/772 comprising A/D, V/T, V/F, I/T or I/F converters
• CPC Class Codes: H04N 25/778 comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself

Abstract

The present technology relates to a solid-state imaging device and an electronic device that enable a reduction in the voltage of an AD conversion circuit. A solid-state imaging device includes: a plurality of pixels; a vertical signal line configured to output a pixel signal of the pixel; and a clipping circuit configured to limit a voltage of the vertical signal line to a predetermined voltage. The clipping circuit includes a transistor configured to generate the predetermined voltage in accordance with a voltage of a gate, and a sample holding circuit configured to hold a reset level of the pixel that is output to the vertical signal line, and input the reset level to the gate of the transistor. The present technology can be applied to a CMOS image sensor, for example.

Claims

1. A solid-state imaging device comprising:

a plurality of pixels;

a vertical signal line configured to output a pixel signal of the pixel; and

a clipping circuit configured to limit a voltage of the vertical signal line to a predetermined voltage,

wherein the clipping circuit includes

a transistor configured to generate the predetermined voltage in accordance with a voltage of a gate, and

a sample holding circuit configured to hold a reset level of the pixel that is output to the vertical signal line, and input the reset level to the gate of the transistor.

2. The solid-state imaging device according to claim 1,

wherein the clipping circuit further includes a capacitor having one electrode connected to the gate of the transistor, and

a voltage generation circuit configured to generate a plurality of different voltages is connected to the other electrode of the capacitor.

3. The solid-state imaging device according to claim 2,

wherein the voltage generation circuit applies different voltages to the capacitor between in reading the reset level of the pixel and in reading a signal level of the pixel.

4. The solid-state imaging device according to claim 2,

wherein the clipping circuit includes a plurality of the capacitors, and

the voltage generation circuit applies a first voltage to one capacitor in reading the reset level of the pixel, and applies a second voltage to another capacitor in reading a signal level of the pixel.

5. The solid-state imaging device according to claim 1,

wherein the clipping circuit further includes a selector configured to turn on/off a limitation on the voltage of the vertical signal line using the predetermined voltage generated by the transistor.

6. An electronic device comprising

a solid-state imaging device including

a plurality of pixels,

a vertical signal line configured to output a pixel signal of the pixel, and

a clipping circuit configured to limit a voltage of the vertical signal line to a predetermined voltage,

wherein the clipping circuit includes

a transistor configured to generate the predetermined voltage in accordance with a voltage of a gate, and

a sample holding circuit configured to hold a reset level of the pixel that is output to the vertical signal line, and input the reset level to the gate of the transistor.