INTERLEVEL CONNECTORS IN MULTILEVEL CIRCUITRY, AND METHOD FOR FORMING THE SAME
First Claim
1. A 3D circuit, comprising:
- multilevel circuitry having circuit elements disposed in a set of levels including W levels L(i) for i going from 1 to W, the multilevel circuitry including a multilevel region having a perimeter having a plurality of sides, and a set of contact regions including N members, the contact regions in the set of contact regions being disposed on different sides of the plurality of sides of the perimeter of the multilevel region; and
each contact region in the set of contact regions including landing areas on circuit elements in up to M levels of the multilevel circuitry, where a first subset of the contact regions disposed on a first side of the perimeter includes landing areas only on uppermost levels L(i) for i going from W−
M+1 to W, and a second subset of the contact regions disposed on a second side of the perimeter, includes landing areas only on levels L(i), for i going from W−
M+1−
S1 to W−
S1.
1 Assignment
0 Petitions
Accused Products
Abstract
Multilevel circuitry such as a a 3D memory array, has a set of contact regions arranged around a perimeter of a multilevel region, in which connection is made to circuit elements in a number W levels. Each of the contact regions has a number of steps having landing areas thereon, including steps on up to a number M levels, where the number M can be much less than W. A combination of contact regions provides landing areas on all of the W levels, each of the contact regions in the combination having landing areas on different subsets of the W levels. A method of forming the device uses an etch-trim process to form M levels in all of the contact regions, and one or more anisotropic etches in some of the contact regions.
-
Citations
20 Claims
-
1. A 3D circuit, comprising:
-
multilevel circuitry having circuit elements disposed in a set of levels including W levels L(i) for i going from 1 to W, the multilevel circuitry including a multilevel region having a perimeter having a plurality of sides, and a set of contact regions including N members, the contact regions in the set of contact regions being disposed on different sides of the plurality of sides of the perimeter of the multilevel region; and each contact region in the set of contact regions including landing areas on circuit elements in up to M levels of the multilevel circuitry, where a first subset of the contact regions disposed on a first side of the perimeter includes landing areas only on uppermost levels L(i) for i going from W−
M+1 to W, and a second subset of the contact regions disposed on a second side of the perimeter, includes landing areas only on levels L(i), for i going from W−
M+1−
S1 to W−
S1. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
-
-
11. A method for manufacturing 3D circuitry, comprising:
-
forming multilevel circuitry having circuit elements disposed in a set of levels including W levels, the multilevel circuitry including a multilevel region having a perimeter having a plurality of sides, and a set of contact regions including N members, the contact regions in the set of contact regions being disposed on different sides of the plurality of sides of the perimeter of the multilevel region; performing an etch-trim process to form M steps in each of the N members of the set of contact regions, where the etch-trim process includes at least one etch-trim cycle and the etch-trim cycle includes forming an etch-trim mask exposing portions of the set of contact regions, and iteratively etching one level of the set of levels using the etch-trim mask, and then trimming the etch-trim mask in the set of contact regions and etching one more level using the trimmed etch-trim mask for a number of iterations; and forming a step mask exposing a subset of the set of contact regions disposed on a first side of the perimeter and covering the multilevel region and all other contact regions in the set of contact regions, and etching S1 levels using the step mask, wherein the subset includes less than N members of the set of contact regions, whereby landing areas on circuit elements in S1+M levels in the set of levels are formed in the set of contact regions, and wherein landing areas on no more than M levels are formed in one contact region in the set of contact regions. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
-
Specification