INTERLEVEL CONNECTORS IN MULTILEVEL CIRCUITRY, AND METHOD FOR FORMING THE SAME

• US 20180102281A1
• Filed: 10/10/2016
• Published: 04/12/2018
• Est. Priority Date: 10/10/2016
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Yang, Chin-Cheng
• Granted Patent: US 10,446,437 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/41 of a memory region comprising a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/50 characterised by the boundary region between the core region and the peripheral circuit region
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

Multilevel circuitry such as a a 3D memory array, has a set of contact regions arranged around a perimeter of a multilevel region, in which connection is made to circuit elements in a number W levels. Each of the contact regions has a number of steps having landing areas thereon, including steps on up to a number M levels, where the number M can be much less than W. A combination of contact regions provides landing areas on all of the W levels, each of the contact regions in the combination having landing areas on different subsets of the W levels. A method of forming the device uses an etch-trim process to form M levels in all of the contact regions, and one or more anisotropic etches in some of the contact regions.

Claims

1. A 3D circuit, comprising:

multilevel circuitry having circuit elements disposed in a set of levels including W levels L(i) for i going from 1 to W, the multilevel circuitry including a multilevel region having a perimeter having a plurality of sides, and a set of contact regions including N members, the contact regions in the set of contact regions being disposed on different sides of the plurality of sides of the perimeter of the multilevel region; and

each contact region in the set of contact regions including landing areas on circuit elements in up to M levels of the multilevel circuitry, where a first subset of the contact regions disposed on a first side of the perimeter includes landing areas only on uppermost levels L(i) for i going from W−

M+1 to W, and a second subset of the contact regions disposed on a second side of the perimeter, includes landing areas only on levels L(i), for i going from W−

M+1−

S1 to W−

S1.

2. The 3D circuit of claim 1, wherein a third subset of the contact regions including at least one disposed on a third side of the perimeter includes landing areas on levels L(i), for i going from W−

M+1−

S1−

52 to W−

S1−

S2.

3. The 3D circuit of claim 1, wherein a fourth subset of the contact regions including at least one disposed on a fourth side of the perimeter includes landing areas on levels L(i), for i going from W−

M+1−

S1−

S2−

S3 to W−

S1−

S2−

S3.

4. The 3D circuit of claim 1, wherein in the contact regions in the set of contact regions, the circuit elements in the levels comprise conductors in a layer of conductive material and a layer of insulating material, further comprising:

a dielectric fill over the landing areas;

contact openings down to the landing areas through the dielectric fill; and

interlevel connectors in the contact openings.

5. The 3D circuit of claim 1, wherein the landing areas step sequentially to lower levels in a direction orthogonal to the perimeter in each of contact regions in the set of contact regions.

6. The 3D circuit of claim 1, wherein the members of the set of contact regions have a uniform width dimension orthogonal to the corresponding sides.

7. The 3D circuit of claim 6, wherein the M steps in the contact regions have in combination a stairstep width in the dimension orthogonal to the corresponding sides, and the uniform width of the contact regions in the set of contact regions is equal to said stairstep width plus a process margin, the process margin being less than said stairstep width.

8. The 3D circuit of claim 1, wherein the multilevel circuitry comprises a 3D memory array.

9. The 3D circuit of claim 1, wherein the multilevel region includes a transition region including only conductors between circuit elements in the multilevel circuitry and the contact regions, and the perimeter is in the transition region.

10. The 3D circuit of claim 1, wherein the multilevel region includes a transition region including only conductors between circuit elements in the multilevel circuitry and the contact regions, and the perimeter is in the transition region and comprises four sides, and contact regions in the set of contact regions have sides disposed on the perimeter on each of said four sides.

11. A method for manufacturing 3D circuitry, comprising:

forming multilevel circuitry having circuit elements disposed in a set of levels including W levels, the multilevel circuitry including a multilevel region having a perimeter having a plurality of sides, and a set of contact regions including N members, the contact regions in the set of contact regions being disposed on different sides of the plurality of sides of the perimeter of the multilevel region;

performing an etch-trim process to form M steps in each of the N members of the set of contact regions, where the etch-trim process includes at least one etch-trim cycle and the etch-trim cycle includes forming an etch-trim mask exposing portions of the set of contact regions, and iteratively etching one level of the set of levels using the etch-trim mask, and then trimming the etch-trim mask in the set of contact regions and etching one more level using the trimmed etch-trim mask for a number of iterations; and

forming a step mask exposing a subset of the set of contact regions disposed on a first side of the perimeter and covering the multilevel region and all other contact regions in the set of contact regions, and etching S1 levels using the step mask, wherein the subset includes less than N members of the set of contact regions, whereby landing areas on circuit elements in S1+M levels in the set of levels are formed in the set of contact regions, and wherein landing areas on no more than M levels are formed in one contact region in the set of contact regions.

12. The method of claim 11, further comprising:

forming a second step mask exposing a second subset of the set of contact regions disposed on a second side of the perimeter and covering the multilevel region and all other contact regions in the set of contact regions, and etching S2 levels using the second step mask, wherein the second subset and the first mentioned subset are not equal sets, and intersect with at least one of the N members of the set of contact regions,

whereby landing areas on circuit elements in S1+S2+M levels in the set of levels are formed in the set of contact regions.

13. The method of claim 11, further comprising:

forming a third step mask exposing a third subset of the set of contact regions disposed on a third side of the perimeter and covering the multilevel region and all other contact regions in the set of contact regions, and etching S3 levels using the third step mask, wherein the third subset is not an equal set with the first mentioned subset and is not an equal set with the second subset, and the third subset includes a member of the set of contact regions that is in both the first mentioned and the second subsets,

whereby landing areas on circuit elements in S1+S2+S3+M levels in the set of levels are formed in the set of contact regions.

14. The method of claim 11, wherein in the contact regions in the set of contact regions, the levels comprise a layer of conductive material and a layer of insulating material, further comprising:

after said landing areas are formed, applying a dielectric fill over the landing areas;

creating contact openings down to the landing areas through the dielectric fill; and

forming interlevel connectors in the contact openings.

15. The method of claim 11, wherein M is greater than 10.

16. The method of claim 11, wherein contact regions in the set of contact regions have a uniform width dimension orthogonal to the corresponding sides.

17. The method of claim 16, wherein the M steps formed in the etch-trim process have in combination a stairstep width in the dimension orthogonal to the corresponding sides, and the uniform width of the contact regions in the set of contact regions is equal to said stairstep width plus a process margin, the process margin being less than said stairstep width.

18. The method of claim 11, wherein the etch-trim process includes more than one etch-trim cycle using more than one etch-trim mask.

19. The method of claim 11, wherein the multilevel circuitry comprises a 3D memory array.

20. The method of claim 11, wherein said forming multilevel circuitry includes forming a layer of insulating mater and a layer of sacrificial material in each of said levels, and replacing at least parts of the sacrificial material in each of said levels with a conductor material;

applying a dielectric fill over the landing areas after said replacing;

creating contact openings down to conductive material in the landing areas through the dielectric fill; and

forming interlevel connectors in the contact openings.