REDUCING METAL GATE OVERHANG BY FORMING A TOP-WIDE BOTTOM-NARROW DUMMY GATE ELECTRODE

• US 20180102418A1
• Filed: 01/31/2017
• Published: 04/12/2018
• Est. Priority Date: 10/07/2016
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Bih, Shih Wei, Liao, Han-Wen, Yan, Xuan-You, Chen, Yen-Yu, Lin, Chun-Chih
• Granted Patent: US 10,446,662 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/32135 by vapour etching only
• CPC Class Codes: H01L 21/32137 of silicon-containing layers
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

A polysilicon layer is formed over a substrate. The polysilicon layer is etched to form a dummy gate electrode having a top portion with a first lateral dimension and a bottom portion with a second lateral dimension. The first lateral dimension is greater than, or equal to, the second lateral dimension. The dummy gate electrode is replaced with a metal gate electrode.

Claims

1. A method of fabricating a semiconductor device, the method comprising:

forming a polysilicon layer over a substrate;

etching the polysilicon layer to form a dummy gate electrode having a top portion with a first lateral dimension and a bottom portion with a second lateral dimension, the first lateral dimension being greater than, or equal to, the second lateral dimension; and

replacing the dummy gate electrode with a metal gate electrode.

2. The method of claim 1, further comprising:

before the forming of the polysilicon layer, forming a high-k gate dielectric layer over the substrate, wherein the polysilicon layer is formed over the high-k gate dielectric layer.

3. The method of claim 1, further comprising, before the replacing of the dummy gate electrode:

forming spacers on sidewalls of the dummy gate electrode;

forming source/drain regions in the substrate on opposite sides of the dummy gate electrode; and

forming an interlayer dielectric (ILD) over the substrate.

4. The method of claim 1, wherein:

the top portion of the dummy gate electrode is formed when the etching is performed with a first lateral etching rate; and

the bottom portion of the dummy gate electrode is formed when the etching is performed with a second lateral etching rate greater than the first lateral etching rate.

5. The method of claim 1, wherein the etching comprises using a fluorine-containing etchant, and wherein the etching is performed by increasing a fluorine content of the etchant as the etching progresses deeper into the polysilicon layer.

6. The method of claim 5, wherein the increasing the fluorine content comprises increasing a flow rate of the fluorine-containing etchant.

7. The method of claim 6, wherein the flow rate is in a range between about 80 sccm and about 120 sccm.

8. The method of claim 5, wherein the etching comprises applying a chorine-containing etchant simultaneously with the fluorine-containing etchant.

9. The method of claim 1, wherein the etching comprises applying a passivation gas when the top portion of the dummy gate electrode is etched.

10. The method of claim 1, wherein the etching is performed such that the dummy gate electrode has a cross-sectional profile that resembles an upside-down trapezoid.

11. The method of claim 1, wherein the first lateral dimension is greater than the second lateral dimension by at least 20%.

12. A method of fabricating a semiconductor device, the method comprising:

forming a gate dielectric layer over a substrate;

forming a dummy gate electrode layer over the gate dielectric layer;

etching the dummy gate electrode layer with an etchant that contains fluorine and chlorine to form a dummy gate electrode, wherein the etching comprising increasing a fluorine content of the etchant as the etching progresses deeper into the dummy gate electrode layer;

forming spacers on sidewalls of the dummy gate electrode;

forming source/drain regions in the substrate on opposite sides of the dummy gate electrode; and

replacing the dummy gate electrode with a metal gate electrode.

13. The method of claim 12, wherein the increasing the fluorine content is performed such that a top portion of the dummy gate electrode is wider than a bottom portion of the dummy gate electrode.

14. The method of claim 12, wherein the etching is performed such that the dummy gate electrode has a cross-sectional profile that resembles an upside-down trapezoid.

15. The method of claim 12, wherein:

the etchant includes a fluorine-containing etchant and a chlorine-containing etchant; and

the increasing the fluorine content comprises increasing a flow rate of the fluorine-containing etchant.

16. The method of claim 12, wherein the etching further comprises applying a passivation gas when a top portion of the dummy gate electrode is formed.

17-20. -20. (canceled)

21. A method of fabricating a semiconductor device, comprising:

forming a dummy gate electrode layer over a substrate;

etching the dummy gate electrode layer to form a dummy gate electrode having a top-wide bottom-narrow profile in a cross-sectional view; and

replacing the dummy gate electrode with a metal gate electrode.

22. The method of claim 21, wherein the etching is performed with different etching rates as different portions of the dummy gate electrode layer are being etched.

23. The method of claim 21, wherein the etching is performed by increasing a fluorine content of an etchant or increasing a flow rate of the etchant as deeper portions of the dummy gate electrode layer are being etched.

24. The method of claim 21, wherein the etching further comprises applying a chlorine-containing etchant.