Structure and Method for FinFET Device with Buried Sige Oxide

• US 20180102419A1
• Filed: 12/12/2017
• Published: 04/12/2018
• Est. Priority Date: 11/26/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Ching, Kuo-Cheng, Diaz, Carlos H., Wang, Chih-Hao, Wu, Zhiqiang
• Granted Patent: US 10,804,381 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/02236 group IV semiconductor
• CPC Class Codes: H01L 21/02255 formation by thermal treatment H01L21/02252 takes precedence; after treatment of an insulating film H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/2255 the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
• CPC Class Codes: H01L 21/28167 on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66803 with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
• CPC Class Codes: H01L 29/66818 the channel being thinned after patterning, e.g. sacrificial oxidation on fin
• CPC Class Codes: H01L 29/7849 the means being provided under the channel
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor device includes a substrate and a fin feature over the substrate. The fin feature includes a first portion having a first semiconductor material and a second portion having a second semiconductor material over the first portion. The second semiconductor material is different from the first semiconductor material. The semiconductor device further includes an isolation feature over the substrate and over sides of the fin feature; a semiconductor oxide feature including the first semiconductor material and disposed on sidewalls of the first portion; and a gate stack disposed on the fin feature and the isolation feature. The gate stack includes a gate dielectric layer extending into recesses that are into a top portion of the semiconductor oxide feature and below the second portion of the fin feature.

Claims

1. A semiconductor device, comprising:

a substrate;

a fin feature over the substrate, wherein the fin feature includes a first portion having a first semiconductor material and a second portion having a second semiconductor material over the first portion, wherein the second semiconductor material is different from the first semiconductor material;

an isolation feature over the substrate and over sides of the fin feature;

a semiconductor oxide feature including the first semiconductor material and disposed on sidewalls of the first portion; and

a gate stack disposed on the fin feature and the isolation feature, wherein the gate stack includes a gate dielectric layer extending into recesses that are into a top portion of the semiconductor oxide feature and below the second portion of the fin feature.

2. The semiconductor device of claim 1, wherein the sidewalls of the first portion are recessed.

3. The semiconductor device of claim 1, wherein the fin feature further includes a third portion below the first portion, and the third portion includes the second semiconductor material.

4. The semiconductor device of claim 1, wherein the isolation feature includes an edge portion contacting a sidewall of the semiconductor oxide feature, and the edge portion has a top surface below a top surface of the first portion of the fin feature.

5. The semiconductor device of claim 4, wherein the isolation feature further includes another portion adjacent to the edge portion, and the another portion has another top surface above the top surface of the first portion of the fin feature.

6. The semiconductor device of claim 1, wherein the first semiconductor material includes silicon germanium and the second semiconductor material include silicon.

7. The semiconductor device of claim 1, wherein the semiconductor oxide feature includes silicon germanium oxide or germanium oxide, and the gate dielectric layer includes a high-k dielectric material.

8. The semiconductor device of claim 1, wherein the gate stack further includes a gate electrode disposed on the gate dielectric layer and the gate electrode includes a metal.

9. The semiconductor device of claim 8, wherein a portion of the gate electrode also extends into the recesses.

10. A semiconductor structure, comprising:

an isolation feature over a substrate;

a fin feature over the substrate and surrounded by the isolation feature, wherein the fin feature includes a first portion having a first semiconductor material and a second portion having a second semiconductor material over the first portion, wherein the first semiconductor material has a first lattice constant and the second semiconductor material has a second lattice constant different from the first lattice constant;

a semiconductor oxide feature over a concave sidewall of the first portion of the fin feature; and

a gate stack extending from a top surface of the fin feature to below the second portion of the fin feature, wherein the gate stack includes a gate dielectric layer extending into a dented space defined in a top portion of the semiconductor oxide feature.

11. The semiconductor structure of claim 10, wherein a top surface of the isolation feature is above a top surface of the first portion of the fin feature.

12. The semiconductor structure of claim 11, wherein an edge portion of the isolation feature is in physical contact with the semiconductor oxide feature and is below the top surface of the first portion of the fin feature.

13. The semiconductor structure of claim 10, wherein the semiconductor oxide feature extends in vertical direction from a top surface of the first portion of the fin feature to a bottom surface of the first portion of the fin feature.

14. The semiconductor structure of claim 10, wherein the dented space extends a vertical dimension ranging from about 3 nm to about 6 nm and a horizontal dimension ranging from about 1 nm to about 4 nm.

15. The semiconductor structure of claim 10, wherein the gate stack further includes a gate electrode disposed on the gate dielectric layer and the gate electrode also extends into the dented space.

16. A semiconductor device, comprising:

a substrate;

a fin feature on the substrate, wherein the fin feature includes a first portion and a second portion over the first portion;

a semiconductor oxide feature disposed on recessed sidewalls of the first portion; and

a gate disposed on the fin feature, wherein the gate includes a gate dielectric layer, and corner portions of the gate dielectric layer extend inwardly into the semiconductor oxide feature and are below the second portion of the fin feature.

17. The semiconductor device of claim 16, wherein the first portion includes silicon germanium, the second portion includes silicon, the semiconductor oxide feature includes silicon germanium oxide, and the gate dielectric layer includes a high-k dielectric material.

18. The semiconductor device of claim 16, wherein each of the corner portions extends a vertical dimension ranging from about 1 nm to about 4 nm and a horizontal dimension ranging from about 1 nm to about 4 nm.

19. The semiconductor device of claim 16, wherein the gate further includes a gate electrode layer, and portions of the gate electrode layer bend horizontally into the corner portions.

20. The semiconductor device of claim 16, wherein the gate dielectric layer includes an interfacial layer and a high-k dielectric layer over the interfacial layer, wherein the corner portions are free of the interfacial layer.