Power MOSFET With Metal Filled Deep Sinker Contact For CSP

• US 20180102424A1
• Filed: 12/04/2017
• Published: 04/12/2018
• Est. Priority Date: 06/30/2016
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: XIONG, Yufei, LIU, Yunlong, YANG, Hong, LIN, Ho, LV, Tian Ping, ZOU, Sheng, JIA, Qiu Ling
• Granted Patent: US 10,903,345 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/283 Deposition of conductive or insulating materials for electrodes conducting electric current
• CPC Class Codes: H01L 21/3213 Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/405 Resistive arrangements, e.g. resistive or semi-insulating field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/7396 with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7398 with both emitter and collector contacts in the same substrate side
• CPC Class Codes: H01L 29/7809 having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

A method of forming an IC including a power semiconductor device includes providing a substrate having an epi layer thereon with at least one transistor formed therein covered by a pre-metal dielectric (PMD) layer. Contact openings are etched from through the PMD into the epi layer to form a sinker trench extending to a first node of the device. A metal fill material is deposited to cover a sidewall and bottom of the sinker trench but not completely fill the sinker trench. A dielectric filler layer is deposited over the metal fill material to fill the sinker trench. An overburden region of the dielectric filler layer is removed stopping on a surface of the metal fill material in the overburden region to form a sinker contact. A patterned interconnect metal is formed providing a connection between the interconnect metal and metal fill material on the sidewall of the sinker trench.

Claims

1. A semiconductor device comprising:

a substrate;

an epitaxial (epi) layer disposed over the substrate, the epi layer including a well region;

a pre-metal dielectric layer disposed over the epi layer;

a first device terminal;

a second device terminal disposed at least partially within the well region;

a third device terminal; and

a contact comprising;

a trench having a first portion that extends through the pre-metal dielectric layer and a second portion that extends through at least a portion of the epi layer to provide an electrical connection to the third device terminal;

a metal fill material disposed in the trench but not completely filling the second portion of the trench; and

an inner dielectric filler layer disposed over the metal fill material and filling the trench.

2. The semiconductor device of claim 1, wherein the metal fill material comprises at least one of tungsten (W), copper (Cu), platinum (Pt), palladium (Pd), or a titanium alloy.

3. The semiconductor device of claim 1, wherein the dielectric filler layer comprises a sintered spin on glass (SOG) coating that has micro-porosity.

4. The semiconductor device of claim 1, wherein the second portion of the trench extends at least through the epi layer to an interface between the epi layer and the substrate.

5. The semiconductor device of claim 4, wherein the second portion of the trench extends into substrate.

6. The semiconductor device of claim 1, wherein the second portion of the trench does not extend completely through the epi layer and the bottom of the trench and an interface between the epi layer and the substrate are separated by a distance.

7. The semiconductor device of claim 6, wherein the epi layer is at least 5 μ

m thick and the distance separating the bottom of the trench and the interface is between 0.5 μ

m and 1 μ

m.

8. The semiconductor device of claim 1, wherein:

the epi layer is of a first conductivity type;

the first device terminal includes a diffusion region of the first conductivity type disposed in the well region; and

the well region is of a second conductivity type that is opposite the first conductivity type.

9. The semiconductor device of claim 8, wherein the first conductivity type is n-type and the second conductivity type is p-type.

10. The semiconductor device of claim 1, comprising a dielectric layer formed at least partially in the well region and electrically isolating the second device terminal from the first device terminal.

11. The semiconductor device of claim 1, wherein the metal fill material covers both a sidewall of the trench and a bottom of the trench.

12. The semiconductor device of claim 11, comprising a barrier metal liner disposed between the metal fill material and the sidewall and the bottom of the trench.

13. The semiconductor device of claim 12, wherein the barrier metal liner includes a first layer of titanium nitride (TiN) and a second layer of titanium (Ti) disposed over the first layer, the first and second layers arranged as a stack.

14. A method of forming an integrated circuit (IC) including a semiconductor device, the method comprising:

forming a transistor in an epitaxial (epi) layer disposed over a substrate;

forming a pre-metal dielectric layer over the epitaxial layer and covering the transistor;

etching a first contact opening through the pre-metal dielectric layer and through at least a portion of the epi layer to form a trench, wherein the trench includes a sidewall and a bottom and has a first portion that extends through the pre-metal dielectric layer and a second portion that extends through at least a portion of the epi layer;

depositing a metal fill material in the trench so that the metal fill material covers the sidewall and the bottom of the trench, but does not completely fill the second portion of the trench;

depositing a dielectric filler layer over the metal fill material to fill the trench; and

forming a patterned interconnect metal to provide a connection between the interconnect metal and the metal fill material in the trench.

15. The method of claim 14, wherein depositing a dielectric filler layer over the metal fill material to fill the trench comprises removing an overburden region of the dielectric filler layer to form a contact, wherein a portion of the dielectric filler layer remains in the trench after removing the overburden region.

16. The method of claim 14, wherein etching the first contact opening through the pre-metal dielectric layer and through at least a portion of the epi layer to form the trench comprises etching the first contact opening so that the second portion of the trench does not extend completely through the epi layer.

17. The method of claim 14, wherein etching the first contact opening through the pre-metal dielectric layer and through at least a portion of the epi layer to form the trench comprises etching the first contact opening so that the second portion of the trench extends completely through the epi layer and into a portion of the substrate.

18. An integrated circuit (IC) comprising:

a semiconductor device comprising;

a substrate;

an epitaxial (epi) layer disposed over the substrate, the epi layer including a well region;

a pre-metal dielectric layer disposed over the epi layer;

a first device terminal;

a second device terminal disposed at least partially within the well region;

a third device terminal; and

a contact comprising;

a trench having a first portion that extends through the pre-metal dielectric layer and a second portion that extends through at least a portion of the epi layer to provide an electrical connection to the third device terminal;

a metal fill material disposed in the trench but not completely filling the second portion of the trench; and

an inner dielectric filler layer disposed over the metal fill material and filling the trench.

19. The IC of claim 18, wherein the semiconductor device is a metal-oxide-semiconductor field effect transistor (MOSFET) device and the third device terminal is a buried drain.

20. The IC of claim 18, wherein the semiconductor device is a bipolar device and the third device terminal is a buried collector.