CRYOGENIC ELECTRONIC PACKAGES AND METHODS FOR FABRICATING CRYOGENIC ELECTRONIC PACKAGES

• US 20180102469A1
• Filed: 08/23/2017
• Published: 04/12/2018
• Est. Priority Date: 10/11/2016
• Status: Active Grant

• Current Assignee: Massachusetts Institute of Technology
• Original Assignee: Massachusetts Institute of Technology
• Inventors: Das, Rabindra N., Dauler, Eric A.
• Granted Patent: US 10,381,541 B2
• Time in Patent Office: Days
• CPC Class Codes: G06N 10/00 Quantum computing, i.e. information processing based on quantum-mechanical phenomena
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05109 Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/05111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/05116 Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05164 Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05169 Platinum [Pt] as principal constituent
• CPC Class Codes: H01L 2224/05179 Niobium [Nb] as principal constituent
• CPC Class Codes: H01L 2224/05183 Rhenium [Re] as principal constituent
• CPC Class Codes: H01L 2224/05186 with a principal constituent of the material being a non metallic, non metalloid inorganic material
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05609 Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/05611 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05666 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05679 : Niobium [Nb] as principal constituent
• CPC Class Codes: H01L 2224/05686 : with a principal constituent of the material being a non metallic, non metalloid inorganic material
• CPC Class Codes: H01L 2224/10 : Bump connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/131 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13109 : Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/13111 : Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13116 : Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/13139 : Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13179 : Niobium [Nb] as principal constituent
• CPC Class Codes: H01L 2224/136 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16145 : the bodies being stacked
• CPC Class Codes: H01L 2224/17181 : On opposite sides of the body
• CPC Class Codes: H01L 2224/29111 : Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/29116 : Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/29187 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2224/2919 : with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/2929 : with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/293 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/32225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/43848 : Thermal treatments, e.g. annealing, controlled cooling
• CPC Class Codes: H01L 2224/45014 : Ribbon connectors, e.g. rectangular cross-section
• CPC Class Codes: H01L 2224/45124 : Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 : Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 : Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/45179 : Niobium (Nb) as principal constituent
• CPC Class Codes: H01L 2224/48091 : Arched
• CPC Class Codes: H01L 2224/48106 : the connector being orthogonal to a side surface of the semiconductor or solid-state body, e.g. parallel layout
• CPC Class Codes: H01L 2224/48225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48227 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73207 : Bump and wire connectors
• CPC Class Codes: H01L 2224/73253 : Bump and layer connectors
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/85399 : Material
• CPC Class Codes: H01L 2225/0651 : Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06548 : Conductive via connections through the substrate, container, or encapsulation
• CPC Class Codes: H01L 2225/06589 : Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/445 : the fluid being a liquefied gas, e.g. in a cryogenic vessel
• CPC Class Codes: H01L 23/49811 : Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49888 : the conductive materials containing superconducting material
• CPC Class Codes: H01L 23/5384 : Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/5385 : Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 23/5386 : Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/167 : comprising optoelectronic devices, e.g. LED, photodiodes
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01041 : Niobium [Nb]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/013 : Alloys
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/0494 : 4th Group
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/0495 : 5th Group
• CPC Class Codes: H01L 2924/0509 : being a combination of two or more materials provided in the groups H01L2924/0491 - H01L2924/0506
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/10271 : Silicon-germanium [SiGe]
• CPC Class Codes: H01L 2924/10272 : Silicon Carbide [SiC]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/1033 : Gallium nitride [GaN]
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13064 : High Electron Mobility Transistor [HEMT, HFET [heterostructure FET], MODFET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01P 7/086 : Coplanar waveguide resonators H01P7/088 takes precedence
• CPC Class Codes: H10N 60/0241 : of devices comprising nitrides or carbonitrides
• CPC Class Codes: H10N 60/0912 : of Josephson-effect devices
• CPC Class Codes: H10N 60/12 : Josephson-effect devices
• CPC Class Codes: H10N 60/805 : for Josephson-effect devices
• CPC Class Codes: H10N 60/815 : for Josephson-effect devices
• CPC Class Codes: H10N 60/82 : Current path
• CPC Class Codes: H10N 60/85 : Superconducting active materials
• CPC Class Codes: H10N 69/00 : Integrated devices, or assemblies of multiple devices, comprising at least one superconducting element covered by group H10N60/00

Abstract

A cryogenic electronic package includes a first superconducting multi-chip module (SMCM), a superconducting interposer, a second SMCM and a superconducting semiconductor structure. The interposer is disposed over and coupled to the first SMCM, the second SMCM is disposed over and coupled to the interposer, and the superconducting semiconductor structure is disposed over and coupled to the second SMCM. The second SMCM and the superconducting semiconductor structure are electrically coupled to the first SMCM through the interposer. A method of fabricating a cryogenic electronic package is also provided.

Claims

1. A cryogenic electronic package, comprising:

a first superconducting multi-chip module (SMCM) having first and second opposing surfaces;

a first superconducting interposer having first and second opposing surfaces, wherein the first surface of the first interposer is disposed over and coupled to the second surface of the first SMCM;

a second SMCM having first and second opposing surfaces, wherein the first surface of the second SMCM is disposed over and coupled to the second surface of the first interposer; and

a first superconducting semiconductor structure having first and second opposing surfaces, wherein the first surface of the first superconducting semiconductor structure is disposed over and coupled to the second surface of the second SMCM, and the second SMCM and the first superconducting semiconductor structure are electrically coupled to the first SMCM through the first interposer.

2. The cryogenic electronic package of claim 1 further comprising:

one or more first interconnect structures disposed between the second surface of the first SMCM and the first surface of the first interposer and coupled to form one or more electrical connections between the first interposer and the first SMCM; and

one or more second interconnect structures disposed between the second surface of the second SMCM and the first surface of the first superconducting semiconductor structure and coupled to form one or more electrical connections between the first superconducting semiconductor structure and the second SMCM, wherein the first interconnect structures have first dimensions and a first pad pitch, and the second interconnect structures have second dimensions and a second pad pitch, wherein the second dimensions are substantially less than the first dimensions, and the second pad pitch is substantially less than the first pad pitch.

3. The cryogenic electronic package of claim 2 wherein each of the first and second interconnect structures includes a plurality of interconnect sections, and at least one of the interconnect sections includes a superconducting and/or a partially superconducting material.

4. The cryogenic electronic package of claim 3 wherein the plurality of interconnect sections includes three interconnect sections, and at least two of the interconnect sections include a plurality of conductive layers, each of the conductive layers including a respective metal or alloy material or combination of materials that is different from other ones of the conductive layers, and each of the conductive layers having a respective melting point that is different from other ones of the conductive layers.

5. The cryogenic electronic package of claim 2 wherein the first SMCM includes one or more interconnect pads disposed or otherwise provided on at least the second surface of the first SMCM, and the first interposer includes one or more interconnect pads disposed or otherwise provide on at least the first surface of the first interposer, wherein the first interconnect structures are electrically coupled to respective ones of the interconnect pads of the first SMCM and the first interposer.

6. The cryogenic electronic package of claim 5 wherein at least one of the interconnect pads of the first SMCM and the first interposer includes a superconducting and/or a partially superconducting material.

7. The cryogenic electronic package of claim 5 wherein the first interposer further includes one or more conventional and/or superconducting and/or partially superconducting metal through via structures, each of the through via structures including a first pad interconnect, a second pad interconnect and a through via, wherein the first and second pad interconnects each extend from selected portions of the first surface of the first interposer to selected portions of the second surface of the first interposer, and the through via is disposed or otherwise provided in a cavity formed between the first and second pad interconnects, wherein the through via structures are electrically coupled to respective ones of the interconnect pads of the first interposer.

8. The cryogenic electronic package of claim 2 wherein the second MCM includes one or more interconnect pads disposed on at least the second surface of the second SMCM, and the first superconducting semiconductor structure includes one or more interconnect pads disposed on at least the first surface of the first superconducting semiconductor structure, wherein the second interconnect structures are electrically coupled to respective ones of the interconnect pads of the second SMCM and the first superconducting semiconductor structure.

9. The cryogenic electronic package of claim 8 wherein at least one of the interconnect pads of the second SMCM and the first superconducting semiconductor structure includes a superconducting and/or a partially superconducting material.

10. The cryogenic electronic package of claim 2 further comprising:

a first adhesive layer disposed between the second surface of the first interposer and the first surface of the second SMCM and coupled to form one or more electrical connections between the second SMCM and the first interposer.

11. The cryogenic electronic package of claim 10 further comprising:

one or more wire and/or ribbon and/or spring bonding structures, wherein at least one of the bonding structures has a first portion electrically coupled to the second surface of the first interposer, and a second opposing portion electrically coupled to the second surface of the second SMCM to form one or more electrical connections between the second SMCM and the first interposer.

12. The cryogenic electronic package of claim 1 further comprising:

a second superconducting interposer having first and second opposing surfaces, wherein the first surface of the second interposer is disposed over and coupled to the second surface of the first SMCM;

a third SMCM having first and second opposing surfaces, wherein the first surface of the third SMCM is disposed over and coupled to the second surface of the second interposer; and

a second superconducting semiconductor structure having first and second opposing surfaces, wherein the first surface of the second superconducting semiconductor structure is disposed over and coupled to the second surface of the third SMCM, and the third SMCM and the second superconducting semiconductor are electrically coupled to the first SMCM through the second interposer, wherein the cryogenic electronic package creates a maximum possible superconducting path between the first and second superconducting semiconductor structures when the first and second superconducting semiconductor structures are electrically coupled with each other through the second SMCM, the first interposer, the first SMCM, the second interposer and the third SMCM.

13. The cryogenic electronic package of claim 1 further comprising:

a third SMCM having first and second opposing surfaces, wherein the first surface of the third SMCM is disposed over and coupled to the second surface of the first interposer; and

a second superconducting semiconductor structure having first and second opposing surfaces, wherein the first surface of the second superconducting semiconductor structure is disposed over and coupled to the second surface of the third SMCM, and the third SMCM and the second superconducting semiconductor are electrically coupled to the first SMCM through the first interposer, wherein the cryogenic electronic package creates a maximum possible superconducting path between the first and second superconducting semiconductor structures when the first and second superconducting semiconductor structures are electrically coupled with each other through the second SMCM, the first interposer, the third SMCM and/or the second SMCM, the first interposer, the first SMCM, the first interposer and the third SMCM.

14. The cryogenic electronic package of claim 13 further comprising:

a via joining layer disposed between the second surface of the first SMCM and the first surface of the first interposer, the via joining layer having first and second opposing surfaces and including a plurality of conductive structures extending between selected portions of the first and second surfaces, wherein the conductive structures are coupled to form one or more electrical connections between the first SMCM and the first interposer, and the conductive structures include one or more thermally conductive vias.

15. The cryogenic electronic package of claim 1 wherein the second SMCM further includes a complementary metal-oxide-semiconductor (CMOS) and/or optical and/or photonics chip.

16. The cryogenic electronic package of claim 1, further comprising:

a substrate having first and second opposing surfaces; and

an adhesive material or layer disposed between the second surface of the substrate and the first surface of the first SMCM, the adhesive layer coupled to form one or more electrical connections between the substrate and the first SMCM.

17. A method of fabricating a cryogenic electronic package, the method comprising:

fabricating a first portion of the cryogenic electronic package through a first process, comprising;

providing a first superconducting multi-chip module (SMCM) having first and second opposing surfaces;

providing a superconducting interposer having first and second opposing surfaces; and

coupling the first surface of the interposer to the second surface of the first SMCM;

fabricating a second portion of the cryogenic electronic package through a second process, comprising;

providing a second SMCM having first and second opposing surfaces;

providing a superconducting semiconductor structure having first and second opposing surfaces; and

coupling the first surface of the superconducting semiconductor structure to the second surface of the second SMCM; and

coupling the second portion of the cryogenic electronic package to the first portion of the cryogenic electronic package.

18. The method of claim 17 wherein coupling the second portion of the cryogenic electronic package to the first portion of the cryogenic electronic package comprises:

disposing an adhesive layer between the first surface of the second SMCM and the second surface of the interposer; and

coupling the first surface of the second SMCM to the second surface of the interposer using the adhesive layer, wherein the first and second processes are performed substantially simultaneously.

19. The method of claim 17 further comprising:

fabricating a third portion of the cryogenic electronic package through a third process, comprising;

providing a substrate having first and second opposing surfaces; and

coupling the third portion of the cryogenic electronic package to the first portion of the cryogenic electronic package.

20. The method of claim 19 wherein coupling the third portion of the cryogenic electronic package to the first portion of the cryogenic electronic package comprises:

disposing an adhesive layer between the first surface of the first SMCM and the second surface of the substrate; and

coupling the first surface of the first SMCM to the second surface of the substrate using the adhesive layer, wherein the first, second and third processes are performed substantially simultaneously.