CRYOGENIC ELECTRONIC PACKAGES AND ASSEMBLIES

• US 20180102470A1
• Filed: 08/23/2017
• Published: 04/12/2018
• Est. Priority Date: 10/11/2016
• Status: Active Grant

• Current Assignee: Massachusetts Institute of Technology
• Original Assignee: Massachusetts Institute of Technology
• Inventors: Das, Rabindra N., Dauler, Eric A.
• Granted Patent: US 10,586,909 B2
• Time in Patent Office: Days
• CPC Class Codes: G06N 10/00 Quantum computing, i.e. information processing based on quantum-mechanical phenomena
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05109 Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/05111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/05116 Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05164 Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05169 Platinum [Pt] as principal constituent
• CPC Class Codes: H01L 2224/05179 Niobium [Nb] as principal constituent
• CPC Class Codes: H01L 2224/05183 Rhenium [Re] as principal constituent
• CPC Class Codes: H01L 2224/05186 with a principal constituent of the material being a non metallic, non metalloid inorganic material
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05609 Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/05611 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05666 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05679 : Niobium [Nb] as principal constituent
• CPC Class Codes: H01L 2224/05686 : with a principal constituent of the material being a non metallic, non metalloid inorganic material
• CPC Class Codes: H01L 2224/10 : Bump connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/131 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13109 : Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/13111 : Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13116 : Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/13139 : Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13179 : Niobium [Nb] as principal constituent
• CPC Class Codes: H01L 2224/136 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16145 : the bodies being stacked
• CPC Class Codes: H01L 2224/17181 : On opposite sides of the body
• CPC Class Codes: H01L 2224/29111 : Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/29116 : Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/29187 : Ceramics, e.g. crystalline carbides, nitrides or oxides glass ceramics H01L2224/29188
• CPC Class Codes: H01L 2224/2919 : with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/2929 : with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/293 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/32225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/43848 : Thermal treatments, e.g. annealing, controlled cooling
• CPC Class Codes: H01L 2224/45014 : Ribbon connectors, e.g. rectangular cross-section
• CPC Class Codes: H01L 2224/45124 : Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 : Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 : Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/45179 : Niobium (Nb) as principal constituent
• CPC Class Codes: H01L 2224/48091 : Arched
• CPC Class Codes: H01L 2224/48106 : the connector being orthogonal to a side surface of the semiconductor or solid-state body, e.g. parallel layout
• CPC Class Codes: H01L 2224/48225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48227 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73207 : Bump and wire connectors
• CPC Class Codes: H01L 2224/73253 : Bump and layer connectors
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/85399 : Material
• CPC Class Codes: H01L 2225/0651 : Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06548 : Conductive via connections through the substrate, container, or encapsulation
• CPC Class Codes: H01L 2225/06589 : Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/445 : the fluid being a liquefied gas, e.g. in a cryogenic vessel
• CPC Class Codes: H01L 23/49811 : Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49888 : the conductive materials containing superconducting material
• CPC Class Codes: H01L 23/5384 : Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/5385 : Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 23/5386 : Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/167 : comprising optoelectronic devices, e.g. LED, photodiodes
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01041 : Niobium [Nb]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/013 : Alloys
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/0494 : 4th Group
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/0495 : 5th Group
• CPC Class Codes: H01L 2924/0509 : being a combination of two or more materials provided in the groups H01L2924/0491 - H01L2924/0506
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/10271 : Silicon-germanium [SiGe]
• CPC Class Codes: H01L 2924/10272 : Silicon Carbide [SiC]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/1033 : Gallium nitride [GaN]
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13064 : High Electron Mobility Transistor [HEMT, HFET [heterostructure FET], MODFET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01P 7/086 : Coplanar waveguide resonators H01P7/088 takes precedence
• CPC Class Codes: H10N 60/0241 : of devices comprising nitrides or carbonitrides
• CPC Class Codes: H10N 60/0912 : of Josephson-effect devices
• CPC Class Codes: H10N 60/12 : Josephson-effect devices
• CPC Class Codes: H10N 60/805 : for Josephson-effect devices
• CPC Class Codes: H10N 60/815 : for Josephson-effect devices
• CPC Class Codes: H10N 60/82 : Current path
• CPC Class Codes: H10N 60/85 : Superconducting active materials
• CPC Class Codes: H10N 69/00 : Integrated devices, or assemblies of multiple devices, comprising at least one superconducting element covered by group H10N60/00

Abstract

A cryogenic electronic package includes a circuitized substrate, an interposer, a superconducting multichip module (SMCM) and at least one superconducting semiconductor structure. The at least one superconducting semiconductor structure is disposed over and coupled to the SMCM, and the interposer is disposed between the SMCM and the substrate. The SMCM and the at least one superconducting semiconductor structure are electrically coupled to the substrate through the interposer. A cryogenic electronic assembly including a plurality of cryogenic electronic packages is also provided.

Claims

1. A cryogenic electronic package, comprising:

a conventional and/or superconducting circuitized substrate having first and second opposing surfaces and including one or more interconnect pads disposed on at least one of the first and second surfaces;

an interposer having first and second opposing surfaces and including one or more interconnect pads disposed on at least one of the first and second surfaces, wherein the first surface of the interposer is disposed over and coupled to the second surface of the substrate;

a first superconducting multichip module (SMCM) having first and second opposing surfaces, wherein the first surface of the first SMCM is disposed over and coupled to the second surface of the interposer; and

at least one first superconducting semiconductor structure having first and second opposing surfaces, wherein the first surface of the at least one first superconducting semiconductor structure is disposed over and coupled to the second surface of the first SMCM, and the first SMCM and the at least one first superconducting semiconductor are electrically coupled to the substrate through the interposer, wherein the interposer redistributes wirings of the first SMCM such that the interposer is capable of utilizing substantially all real estate of the circuitized substrate in order to miniaturize the cryogenic electronic package.

2. The cryogenic electronic package of claim 1 further comprising:

one or more first interconnect structures disposed between the second surface of the substrate and the first surface of the interposer and coupled to respective ones of the interconnect pads provided on the substrate and the interposer to form one or more electrical connections between the interposer and the substrate.

3. The cryogenic electronic package of claim 2 further comprising:

one or more second interconnect structures disposed between the second surface of the first SMCM and the first surface of the at least one first superconducting semiconductor structure and coupled to form one or more electrical connections between the at least one first superconducting semiconductor structure and the first SMCM.

4. The cryogenic electronic package of claim 2 wherein the first interconnect structures form a ball grid array and/or electrically superconductive adhesive array and/or anisotropic superconductive adhesive array assembly on at least one of the substrate and the interposer.

5. The cryogenic electronic package of claim 3 wherein the second interconnect structures form a microbump and/or micropillar and/or fusible metal coated micropillar assembly on at least one of the first SMCM and the at least one first superconducting semiconductor structure.

6. The cryogenic electronic package of claim 3 wherein at least one of the first and second interconnect structures includes at least one superconducting and/or a partially superconducting material.

7. The cryogenic electronic package of claim 3 further comprising:

an adhesive layer disposed between the second surface of the interposer and the first surface of the first SMCM; and

one or more conventional and/or superconducting wire bonding and/or ribbon bonding and/or spring bonding structures, wherein at least one of the bonding structures has a first portion electrically coupled to the second surface of the interposer, and a second opposing portion electrically coupled to the second surface of the first SMCM to form one or more electrical connections between the interposer and the first SMCM.

8. The cryogenic electronic package of claim 3 further comprising:

a first underfill material disposed between the second surface of the substrate and the first surface of the interposer; and

a second underfill material disposed between the second surface of the first SMCM and the first surface of the at least one first superconducting semiconductor structure.

9. The cryogenic electronic package of claim 1 further comprising:

a heat dissipation structure disposed beneath and coupled to the first surface of the substrate; and

a thermal interface structure or material disposed between the heat dissipation structure and the first surface of the substrate.

10. The cryogenic electronic package of claim 1 further comprising:

a second SMCM having first and second opposing surfaces, wherein the first surface of the second SMCM is disposed over and coupled to the second surface of the interposer; and

at least one second superconducting semiconductor structure having first and second opposing surfaces, wherein the first surface of the at least one second superconducting semiconductor structure is disposed over and coupled to the second surface of the second SMCM,

wherein the second SMCM is electrically coupled to the first SMCM through the interposer, and the at least one second superconducting semiconductor structure is electrically coupled to the at least one first superconducting semiconductor structure through the second SMCM, the interposer, and the first SMCM.

11. The cryogenic electronic package of claim 10 further comprising:

one or more third interconnect structures disposed between the second surface of the second SMCM and the first surface of the at least one second superconducting semiconductor structure and coupled to form one or more electrical connections between the at least one second superconducting semiconductor structure and the second SMCM.

12. The cryogenic electronic package of claim 11 wherein the interposer comprises a multi-layer high density superconducting and/or conventional circuitized substrate, and the first and second SMCMs both comprise silicon (Si) based SMCMs.

13. The cryogenic electronic package of claim 12 wherein the at least one first superconducting semiconductor structure and the at least one second superconducting semiconductor structure each comprise a plurality of single-flux-quantum (SFQ) integrated circuits (ICs).

14. The cryogenic electronic package of claim 1 further comprising:

a semiconductor structure joining layer disposed between the second surface of the substrate and the first surface of the interposer, the semiconductor structure joining layer having first and second opposing surfaces and including at least one dielectric material and a plurality of thru-holes extending between selected portions of the first and second surfaces, wherein each of the thru-holes is aligned with a respective one of the interconnect pads provided on the substrate and the interposer, and has a diameter which is greater than a diameter of the respective ones of the interconnect pads to which the thru-holes are aligned with, and wherein each of the thru-holes includes at least a portion of a laminated, electrically superconducting and/or partially superconducting interconnect disposed thereon such that the interconnect substantially fills a respective opening of the thru-hole, and forms one or more electrical connections between the interposer and the substrate.

15. The cryogenic electronic package of claim 14 wherein the thru-holes include at least one superconducting and/or a partially superconducting material.

16. A cryogenic electronic assembly, comprising:

a plurality of cryogenic electronic packages, each comprising;

a substrate having first and second opposing and including one or more interconnect pads disposed on at least one of the first and second surfaces;

an interposer having first and second opposing surfaces and including one or more interconnect pads disposed on at least one of the first and second surfaces;

a superconducting multichip module (SMCM) having first and second opposing surfaces;

at least one superconducting semiconductor structure having first and second opposing surfaces;

one or more first interconnect structures, each of the first interconnect structures disposed between the substrate and the interposer and coupled to respective ones of the interconnected pads disposed on the substrate and the interposer; and

one or more second interconnect structures disposed between the second surface of the SMCM and the first surface of the at least one superconducting semiconductor structure and coupled to form one or more electrical connections between the at least one superconducting semiconductor structure and the SMCM, wherein the at least one superconducting semiconductor structure and the SMCM are electrically coupled to the substrate through the interposer; and

means for electrically coupling the cryogenic electronic packages together.

17. The cryogenic electronic assembly of claim 16 wherein the means for electrically coupling the cryogenic electronic packages together comprises at least one connector having a first and second opposing portions, wherein the first portion of the at least one connector is coupled to a selected one of the interconnect pads provided on the substrate of a first selected one of the cryogenic electronic packages, and the second portion of the at least one connector is coupled to a selected one of the interconnect pads provided on the substrate of a second selected one of second cryogenic electronic packages.

18. The cryogenic electronic assembly of claim 17 wherein the at least one connector comprise at least one of a flex connector, a ribbon connector, a coaxial connector, an optical connector or an optoelectronic connector.

19. The cryogenic electronic assembly of claim 16 wherein the interconnect pads of the substrate are further disposed between the first and second surfaces of the substrate, and the means for electrically coupling the cryogenic electronic packages together comprises at least one conductive structure having a first and second opposing portions, wherein the first portion of the at least one conductive structure is coupled to a selected one of the interconnect pads of the substrate of a first selected one of the cryogenic electronic packages, and the second portion of the at least one conductive structure is coupled to a selected one of the interconnect pads of the substrate of a second selected one of second cryogenic electronic packages.

20. The cryogenic electronic assembly of claim 16 wherein the cryogenic electronic assembly further comprises:

a semiconductor structure having first and second opposing surfaces, wherein the means for electrically coupling the cryogenic electronic packages is provided on the first surface of the semiconductor structure, and the means for electrically coupling the cryogenic electronic packages comprises a plurality of connectors, each of the connectors having a cavity shaped to receive a respective one of the cryogenic electronic packages.

21. The cryogenic electronic assembly of claim 16 wherein the cryogenic electronic packages each further comprise:

an adhesive layer disposed between the second surface of the interposer and the first surface of the SMCM; and

one or more wire bonding structures, wherein at least one of the wire bonding structures has a first portion electrically coupled to the second surface of the interposer, and a second opposing portion electrically coupled to the second surface of the SMCM to form one or more electrical connections between the interposer and the SMCM.

22. The cryogenic electronic assembly of claim 21 wherein the cryogenic electronic packages each further comprise:

a heat dissipation structure disposed beneath and coupled to the first surface of the substrate; and

a thermal interface structure or material disposed between the heat dissipation structure and the first surface of the substrate.

23. The cryogenic electronic assembly of claim 16, wherein the plurality of cryogenic electronic packages includes four cryogenic electronic packages, wherein the first surface of the substrate of a first one of the cryogenic electronic packages is disposed over and coupled to the first surface of the substrate of a second one of the cryogenic electronic packages, and the first surface of the substrate of a third one of the cryogenic electronic packages is disposed over and coupled to the first surface of the substrate of a fourth one of the cryogenic electronic packages.

24. The cryogenic electronic assembly of claim 23, wherein the means for coupling the cryogenic electronic packages together comprises:

a first plurality of conductive structures for coupling the first one of the cryogenic electronic packages to the second one of the cryogenic electronic packages, a second plurality of conductive structures for coupling the third one of the cryogenic electronic packages to the fourth one of the cryogenic electronic packages, and a connector for coupling the first and second ones of the cryogenic electronic packages to the third and fourth ones of the cryogenic electronic packages.