PHASE CONTROL OF CLOCK SIGNAL BASED ON FEEDBACK

• US 20180102779A1
• Filed: 10/06/2016
• Published: 04/12/2018
• Est. Priority Date: 10/06/2016
• Status: Active Grant

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Behel, John Kevin, Nelson, Reuben Pascal, McShea, Matthew D., Courcy, Matthew Louis, Gentile, Kenny, Speir, Carroll C.
• Granted Patent: US 10,305,495 B2
• Time in Patent Office: Days
• CPC Class Codes: H03K 5/1508 using a plurality of delay lines
• CPC Class Codes: H03L 7/06 using a reference signal applied to a frequency- or phase-locked loop
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H04L 7/02 Speed or phase control by the received code signals, the signals containing no special synchronisation information H04L7/0075 takes precedence

Abstract

Aspects of this disclosure relate to adjusting a phase of a clock signal provided to a device based on a feedback signal from the device. The feedback signal can provide phase information associated with the device and/or other information associated with the device, such as temperature information. A feedback signal processor can compute a phase control signal based on the feedback signal. The phase control signal can be used to adjust the phase of the clock signal. By adjusting the phase of one or more clock signals, several devices, such as data converters, can be synchronized.

Claims

1. A system with clock signal phase adjustment, the system comprising:

a device configured to receive a clock signal and to provide a feedback signal, wherein a phase associated with the device is based on the clock signal; and

a clock generator configured to provide the clock signal, the clock generator comprising;

a feedback signal processor configured to receive the feedback signal from the device and to compute a phase control signal based on the feedback signal; and

a clock generating circuit configured to adjust the phase of the clock signal based on the phase control signal.

2. The system of claim 1, wherein the feedback signal comprises information indicative of the phase associated with the device.

3. The system of claim 2, wherein the feedback signal processor comprises:

a phase processor configured to generate a digital signal indicative of the phase associated with the device based on the feedback signal; and

a calculation circuit configured to compute the phase control signal based on the digital signal.

4. The system of claim 3, wherein the phase processor comprises a time-to-digital converter.

6. The system of claim 1, further comprising a second device configured to receive a second clock signal from the clock generator and to provide a second feedback signal to the clock generator, wherein the feedback signal processor comprises a calculation circuit configured to compute the phase control signal based on the feedback signal and the second feedback signal.

7. The system of claim 1, further comprising three other devices configured to receive respective clock signals from the clock generator and to provide respective feedback signals to the clock generator, wherein the clock generator is configured to adjust a phase of the respective clock signal of at least one of the three other devices based on the feedback signal from another of the three other devices.

8. The system of claim 1, wherein the clock signal is a device clock signal, and wherein the clock generator comprises a bi-directional interface configured to receive the feedback signal from the device and to provide a system reference signal to the device.

9. The system of claim 1, wherein the device comprises a data converter, wherein the clock signal is a device clock signal, and wherein the clock generator is configured to provide a system reference signal to the device.

10. The system of claim 1, wherein the feedback signal comprises data information associated with the device.

11. The system of claim 1, wherein the feedback signal processor comprises a calculation circuit configured to compute the phase control signal based on information indicative of temperature.

12. The system of claim 1, wherein the clock generating circuit comprises a phase-locked loop configured to receive the phase control signal and to adjust the phase of the clock signal.

13. The system of claim 1, wherein the clock generating circuit comprises a clock signal path configured to receive the phase control signal and to adjust a delay in the clock signal path to adjust the phase of the clock signal.

5. The system of Claim I, further comprising a second device configured to receive a second clock signal from the clock generator, wherein the clock generator is further configured to receive a second feedback signal from the second device and to adjust a phase of the second clock signal based on the second feedback signal.

14. A feedback signal processor for providing a phase control signal for adjusting a phase of a clock signal, the feedback signal processor comprising:

a phase processor configured to;

receive a feedback signal generated by a device that is configured to receive a clock signal; and

generate a digital signal indicative of a phase associated with the device based on the feedback signal, wherein the phase associated with the device depends on the clock signal; and

a calculation circuit configured to compute a phase control signal based on the digital signal and to output the phase control signal for adjusting the phase of the clock signal.

15. The feedback signal processor of claim 14, wherein the phase processor comprises a time-to-digital converter.

16. The feedback signal processor of claim 14, wherein the calculation circuit is configured to compute the phase control signal based on additional information.

17. The feedback signal processor of claim 16, wherein the additional information comprises at least one of temperature information or information associated with another feedback signal from another device.

18. A clock generator comprising:

the feedback signal processor of claim 14; and

a clock generating circuit configured to adjust the phase of the clock signal and to output the clock signal with the adjusted phase to the device.

19. The clock generator of claim 18, wherein the device is a data converter, and wherein the clock generator is configured to output a second dock signal to a second data converter and provide a system reference signal that is source synchronous with the second clock signal to the second device.

20. The clock generator of claim 18, wherein the clock generator is configured to provide other clock signals to other devices and to adjust a phase of at least one of the other clock signals based on feedback from at least one of the other devices.

21. A clock generator with clock signal phase adjustment, the clock generator comprising:

means for generating a phase control signal based on feedback from a device configured to receive a clock signal from the clock generator; and

a clock generating circuit configured to generate the clock signal, adjust a phase of the clock signal based on the phase control signal, and output the clock signal having the adjusted phase.

22. The clock generator of claim 21, wherein the clock generator is configured to provide other clock signals to other devices and to adjust a phase of each of the other clock signals based on feedback signals received from the other devices.