MEMORY MODULE, MEMORY DEVICE, AND PROCESSING DEVICE HAVING A PROCESSOR MODE, AND MEMORY SYSTEM

• US 20180107406A1
• Filed: 05/23/2017
• Published: 04/19/2018
• Est. Priority Date: 10/14/2016
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd., SNU R&DB Foundation (Seoul National University), Wisconsin Alumni Research Foundation (University of Wisconsin System)
• Original Assignee: SNU R&DB Foundation (Seoul National University), Wisconsin Alumni Research Foundation (University of Wisconsin System)
• Inventors: O, SEONG-IL, KIM, Nam Sung, SON, Young-Hoon, KIM, Chan-Kyung, SONG, Ho-Young, AHN, Jung Ho, HWANG, Sang-Joon
• Granted Patent: US 10,416,896 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 13/1673 using buffers
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0683 Plurality of storage devices
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

A memory module includes a memory device, a command/address buffering device, and a processing data buffer. The memory device includes a memory cell array, a first set of input/output terminals, each terminal configured to receive first command/address bits, and a second set of input/output terminals, each terminal configured to receive both data bits and second command/address bits. The command/address buffering device is configured to output the first command/address bits to the first set of input/output terminals. The processing data buffer is configured to output the data bits and second command/address bits to the second set of input/output terminals. The memory device is configured such that the first command/address bits, second command/address bits, and data bits are all used to access the memory cell array.

Claims

1. A memory module comprising:

a memory device including;

a memory cell array;

a first set of input/output terminals, each terminal configured to receive first command/address bits; and

a second set of input/output terminals, each terminal configured to receive both data bits and second command/address bits;

a command/address buffering device configured to output the first command/address bits to the first set of input/output terminals; and

a processing data buffer configured to output the data bits and second command/address bits to the second set of input/output terminals,

wherein the memory device is configured such that the first command/address bits, second command/address bits, and data bits are all used to access the memory cell array.

2. The memory module of claim 1, wherein the memory device further includes a peripheral circuit that includes a command decoder, an address register, and a data I/O buffer, and further comprising:

a selection circuit configured to select whether to send bits received at the second set of input/output terminals to the command decoder and address register, or to the data I/O buffer.

3. The memory module of claim 1, further comprising:

a first bus configured to transfer bits received from a memory controller to the command/address buffering device; and

a second bus configured to transfer bits received from the memory controller to the processing data buffer.

4. The memory module of claim 3, wherein the memory device further includes a selection circuit configured to receive the bits received via the second bus and to select between transferring the received bits via an internal data path or via an internal command/address path to a peripheral circuit of the memory cell array.

5. The memory module of claim 1, wherein the second set of input/output terminals is configured to serve as data terminals during a normal operation mode of the memory module so that the processing data buffer operates as a data buffer, and to serve as command and address terminals during a processor operation mode of the memory module so that the processing data buffer performs arithmetic and/or logical operations on data stored in the memory device.

6. The memory module of claim 5, further comprising a third set of input/output terminals of the memory device connected to the data buffer and configured to serve as data terminals both during the normal operation mode and during the processor operation mode.

7. A memory module, comprising:

a plurality of memory devices, each including;

a memory cell array;

a first set of input/output terminals, each terminal configured to receive first command/address bits; and

a second set of input/output terminals, each terminal configured to receive data bits;

a command/address buffering device configured to output the first command/address bits to the first set of input/output terminals; and

a plurality of processing data buffers, each configured to switch between acting as a data buffer for a respective memory device and acting as a processor for performing processing operations on data received from the respective memory device.

8. The memory module of claim 7, wherein the plurality of processing data buffers are each configured act as a processor after receiving a processor mode entry command from a device external to the memory module.

9. The memory module of claim 7, wherein the processing operations include at least one of arithmetic and logical operations.

10. The memory module of claim 9, wherein the processing operations include graphic data processing, in-memory database data processing, or real-time analysis.

11. The memory module of claim 7, further comprising:

a bus connected between the command/address buffering device and each of the plurality of processing data buffers, for transmitting command and address information between the command/address buffering device and each of the plurality of processing data buffers.

12. The memory module of claim 11, wherein:

the bus is connected to a processor on each of the processing data buffers.

13. The memory module of claim 7, further comprising:

a set of memory module terminals for connecting the memory module to an external device and positioned on one edge of the memory module,

wherein the plurality of processing data buffers are between the set of memory module terminals and the plurality of memory devices.

14. The memory module of claim 13, wherein:

the command/address buffering device is between a first subset of the memory devices and a second subset of the memory devices.

15. The memory module of claim 14, wherein:

the command/address buffering device has the same number of memory devices on either side of the command/address buffering device.

16. The memory module of claim 7, wherein each processing data buffer includes:

a third set of input/output terminals, each terminal configured to receive and transmit command bits; and

a fourth set of input/output terminals, each terminal configured to receive data bits from and send data bits to a respective memory device; and

a fifth set of input/output terminals configured to receive data bits from and send data bits to a respective set of memory module terminals for communicating outside of the memory module.

17. A processing data buffer for a memory module, the processing data buffer comprising:

a data buffer portion;

a processor portion;

a selection circuit connected to the data buffer portion and the processor portion and configured to select between the data buffer portion and the processor portion;

a plurality of first input/output lines connected between the selection circuit and the data buffer portion;

a plurality of second input/output lines connected between the selection circuit and the processor portion;

a first set of input/output terminals connected to the data buffer portion and for communicating to the outside of the processing data buffer; and

a second set of input/output terminals connected to the selection circuit and for communicating to the outside of the processing data buffer.

18. The processing data buffer of claim 17, wherein:

each terminal of the first set of input/output terminals is configured to transfer data bits; and

each terminal of the second set of input/output terminals is configured to transfer data bits.

19. The processing data buffer of claim 18, wherein:

each line of the plurality of first input/output lines is configured to transfer data bits; and

each line of the plurality of second input/output lines is configured to transfer data bits and command/address bits.

20. The processing data buffer of claim 19, wherein:

each terminal of the second set of input/output terminals is configured to also transfer command/address bits.

21-37. -37. (canceled)