APPARATUSES AND METHODS FOR CONFIGURING I/Os OF MEMORY FOR HYBRID MEMORY MODULES
First Claim
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1. A method, comprising:
- receiving, at a memory module, a command initiated by a host device to operate the memory module in a mode that is based at least in part on a power failure event, wherein the mode of operation comprises communicating data from a synchronous dynamic random-access memory (SDRAM) of the memory module to a non-volatile memory (NVM) of the memory module for the power failure event;
transferring the data from the SDRAM to the NVM via a control circuit of the memory module in response to the command; and
programming a mode register of the memory module with information that indicates the mode of operation, wherein the programming is based at least in part on transferring the data from the SDRAM to the NVM.
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Abstract
Apparatuses, hybrid memory modules, memories, and methods for configuring I/Os of a memory for a hybrid memory module are described. An example apparatus includes a non-volatile memory, a control circuit coupled to the non-volatile memory, and a volatile memory coupled to the control circuit. The volatile memory is configured to enable a first subset of I/Os for communication with a bus and enable a second subset of I/O for communication with the control circuit, wherein the control circuit is configured to transfer information between the volatile memory and the non-volatile memory.
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20 Claims
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1. A method, comprising:
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receiving, at a memory module, a command initiated by a host device to operate the memory module in a mode that is based at least in part on a power failure event, wherein the mode of operation comprises communicating data from a synchronous dynamic random-access memory (SDRAM) of the memory module to a non-volatile memory (NVM) of the memory module for the power failure event; transferring the data from the SDRAM to the NVM via a control circuit of the memory module in response to the command; and programming a mode register of the memory module with information that indicates the mode of operation, wherein the programming is based at least in part on transferring the data from the SDRAM to the NVM. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. An apparatus, comprising:
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a synchronous dynamic random-access memory (SDRAM); a non-volatile memory (NVM) coupled with the SDRAM; a control circuit coupled between the NVM and the SDRAM and configured operate in a plurality of modes and to transfer the data from the SDRAM to the NVM via the control circuit in response to a power failure event; and a mode register coupled with the SDRAM and programmable with information that indicates one of the modes of operation based at least in part on the power failure event. - View Dependent Claims (10, 11, 12, 13, 14)
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15. An apparatus, comprising:
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a controller configured to receive a command initiated by a host device to operate in a mode that is based at least in part on a power failure event, wherein the mode of operation comprises communicating data from a synchronous dynamic random-access memory (SDRAM) to a non-volatile memory (NVM) for the power failure event; a plurality of SDRAMs coupled with the control logic; an NVM coupled with the plurality of SDRAMs via the control logic; and a plurality of mode registers coupled with the SDRAMs and programmable with information that indicates the mode of operation of a plurality of modes of operation. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification