MIGRATION OF COMPUTER SYSTEMS

• US 20180107509A1
• Filed: 07/31/2015
• Published: 04/19/2018
• Est. Priority Date: 07/31/2015
• Status: Abandoned Application

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Inventors: Shaw, Adrian, Mallichan, Kate, Plaquin, David
• Application Number:
  US15/573,542
• Publication Number:
  US 20180107509A1
• Time in Patent Office: Days
• CPC Class Codes: G06F 9/4406 Loading of operating system
• CPC Class Codes: G06F 9/4856 resumption being on a different machine, e.g. task migration, virtual machine migration G06F9/5088 takes precedence

Abstract

An example method for migrating a live operating system from a first computing device to a second computing device is provided. The example method comprises (a) providing register values of a processor of a first computing device to a second computing device which is in communication with the first computing device; (b) providing contents of a dynamic random access memory, DRAM, of the first computing device to the second computing device; (c) storing the register values in a protected memory of the second computing device, wherein the protected memory is separate from a memory used by the second computing device during normal operation of the second computing device; (d) storing the contents of the DRAM of the first computing device in a DRAM of the second computing device; and (e) loading the register values from the protected memory to registers of a processor of the second computing device.

Claims

1. A method for migrating a live operating system from a first computing device to a second computing device, the method comprising:

(a) providing register values of a processor of a first computing device to a second computing device which is in communication with the first computing device;

(b) providing contents of a dynamic random access memory, DRAM, of the first computing device to the second computing device;

(c) storing the register values in a protected memory of the second computing device, wherein the protected memory is separate from a memory used by the second computing device during normal operation of the second computing device;

(d) storing the contents of the DRAM of the first computing device in a DRAM of the second computing device; and

(e) loading the register values from the protected memory to registers of a processor of the second computing device.

2. A method in accordance with the method of claim 1, wherein (a) and (b) are performed by a secure code component comprised in the first computing device and (c), (d) and (e) are performed by a secure code component comprised in the second computing device.

3. A method in accordance with the method of claim 2, wherein the secure code component comprised in the first computing device and/or the secure code component comprised in the second computing device comprises one of:

a piece of trusted code, trusted firmware, a trusted execution environment, TEE.

4. A method in accordance with the method of claim 1, further comprising:

receiving, by the first computing device, a migration command, wherein (a) and (b) are performed responsive to the first computing device receiving a migration command; and

receiving, by the second computing device, a migration command, wherein (c) and (d) are performed responsive to the second computing device receiving a migration command.

5. A method in accordance with the method of claim 1, wherein normal operation of the first computing device is suspended during the performing of (a) and (b) and normal operation of the second computing device is suspended during the performing of d and (e).

6. A method in accordance with the method of claim 1, further comprising transitioning the first computing device to a secure operation mode and performing (a) and (b) whilst in the secure operation mode, and transitioning the second computing device to a secure operation mode and performing (c), (d) and (e) whilst in the secure operation mode.

7. A method in accordance with the method of claim 1, further comprising, before the performing of (e), synchronising settings of the processor of the second computing device with settings of the processor of the first computing device.

8. A method in accordance with the method of claim 1, wherein (e) is performed automatically, responsive to the completion of the performance of (c) and (d).

9. A method in accordance with the method of claim 1, wherein:

performing (a) comprises storing register values of the processor of the first computing device in a secure shared memory accessible by the first computing device and the second computing device, and retrieving the stored register values of the processor of the first computing device from the secure shared memory; and

performing (b) comprises storing contents of the DRAM of the first computing device a secure shared memory accessible by the first computing device and the second computing device, and retrieving contents of the DRAM of the first computing device from the secure shared memory.

10. A method in accordance with the method of claim 1, wherein:

performing (a) comprises sending the register values of the processor of the first computing device to the second computing device over a network; and

performing (b) comprises sending the contents of the DRAM of the first computing device to the second computing device over a network.

11. A method in accordance with the method of claim 1, wherein performing (b) comprises providing regions of the address space of the DRAM which contain data and not providing regions of the address space of the DRAM which do not contain data.

12. A method in accordance with the method of claim 1, further comprising providing the contents of a secondary storage associated with and accessible by the first computing device to the second computing device.

13. A method in accordance with the method of claim 12, wherein the secondary storage is encrypted and is also accessible by the second computing device, and wherein providing the contents of the secondary storage to the second computing device comprises providing an encryption key for the secondary storage to the second computing device, to enable the second computing device to decrypt the secondary storage.

14. A source computing device, comprising:

a dynamic random access memory, DRAM, for storing data;

a processor; and

a secure code component to be executed in response to a migration command received by the source computing device;

wherein the secure code component comprises instructions which, when executed, cause the processor to;

make available, to a target computing device, register values of the processor; and

make available, to the target computing device, data stored in the DRAM.

15. A target computing device, comprising:

a dynamic random access memory, DRAM, for storing data;

a processor;

a protected memory which is separate from a memory used by the target computing device during normal operation of the target computing device; and

a secure code component to be executed in response to a migration command received by the target computing device;

wherein the secure code component comprises instructions which, when executed, cause the processor to;

receive register values of a processor of a source computing device;

store the received register values in the protected memory;

receive data stored in the DRAM of a source computing device;

store the received data in a DRAM of the target computing device; and

load the register values from the protected memory to registers of the processor.