ARRAY SUBSTRATE, METHOD FOR DETECTING THE SAME AND DISPLAY DEVICE

• US 20180108314A1
• Filed: 10/04/2017
• Published: 04/19/2018
• Est. Priority Date: 10/13/2016
• Status: Abandoned Application

• Current Assignee: BOE Technology Group Co., Ltd., Hefei Xinsheng Optoelectric Technology Co. Ltd. (BOE Technology Group Co., Ltd.)
• Original Assignee: BOE Technology Group Co., Ltd., Hefei Xinsheng Optoelectric Technology Co. Ltd. (BOE Technology Group Co., Ltd.)
• Inventors: CAO, Chengying, DU, Ruifang
• Application Number:
  US15/724,810
• Publication Number:
  US 20180108314A1
• Time in Patent Office: Days
• CPC Class Codes: G02F 1/133345 Insulating layers G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence
• CPC Class Codes: G02F 1/136254 Checking; Testing
• CPC Class Codes: G02F 1/136259 Repairing; Defects
• CPC Class Codes: G02F 1/136272 Auxiliary lines
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G09G 2320/0693 Calibration of display systems
• CPC Class Codes: G09G 2330/12 Test circuits or failure detection circuits included in a display system, as permanent part thereof
• CPC Class Codes: G09G 3/006 Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays testing individual LED's G01R31/2635; testing lamps G01R31/44; testing of optical features of LCD displays G02F1/1309
• CPC Class Codes: G09G 3/3674 Details of drivers for scan electrodes
• CPC Class Codes: H01L 23/585 comprising conductive layers or plates or strips or rods or rings H01L23/60, H01L23/62, H01L23/64, H01L23/66 take precedence
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement

Abstract

An array substrate, a method for detecting the array substrate and a display device are provided. At least one test line is disposed on the array substrate and the at least one test line and multiple driving-signal traces overlap with each other. A position where one of the driving-signal traces and the test line overlap with each other is short-circuited to provide a driving signal on the driving-signal trace to an external detection device through a corresponding connection terminal electrically connected with one end of the test line, when a test on the driving signal on the driving-signal trace is performed.

Claims

1. An array substrate, comprising:

a display region comprising a plurality of gate lines; and

a non-display region comprising at least one test line, a plurality of driving-signal traces, and a gate driving circuit comprising a plurality of driving-signal output terminals,

wherein a first end of each of the plurality of driving-signal traces is electrically connected with one of the plurality of driving-signal output terminals, a second end of the driving-signal trace is electrically connected with one of the plurality of gate lines, and the at least one test line overlaps with and is insulated from at least one of the plurality of driving-signal traces.

2. The array substrate according to claim 1, further comprising:

a repairing circuit electrically connected with a first end of the at least one test line.

3. The array substrate according to claim 1, wherein, the non-display region further comprises at least one connection terminal configured to be electrically connected with at least one detection terminal on a detection circuit, wherein the at least one connection terminal is electrically connected with a second end of the at least one test line.

4. The array substrate according to claim 1, wherein an angle other than zero degree exists between an extension direction of the at least one test line and an extension direction of each of the plurality of driving-signal traces.

5. The array substrate according to claim 1, further comprising a source-drain electrode layer,

wherein the source-drain electrode layer is located at one side of the array substrate having the plurality of driving-signal traces and is insulated from the plurality of driving-signal traces, and

the at least one test line and the source-drain electrode layer are located at a same layer and are made of a same material.

6. The array substrate according to claim 1, wherein the gate driving circuit comprises a first gate driving sub-circuit and a second gate driving sub-circuit located at both ends of each of the plurality gate lines, respectively, and

each of the at least one test line comprises a first test sub-line and a second test sub-line.

7. The array substrate according to claim 6, further comprising a base substrate, wherein, the display region and the non-display regions are arranged on the base substrate, and an orthographic projection of the first test sub-line on the base substrate is located between an orthographic projection of the first gate driving sub-circuit on the base substrate and orthographic projections of the plurality of gate lines on the base substrate, and an orthographic projection of the second test sub-line on the base substrate is located between an orthographic projection of the second gate driving sub-circuit on the base substrate and orthographic projections of the plurality of gate lines on the base substrate.

8. The array substrate according to claim 1, further comprising:

a first insulation layer located between a layer at which the at least one test line is located and a layer at which the plurality of driving-signal traces are located.

9. The array substrate according to claim 1, further comprising:

a second insulation layer located above the at least one test line and made of a material with a waterproof function.

10. The array substrate according to claim 9, wherein the gate driving circuit comprises a plurality of shift registers cascaded to form a plurality of stages, each of the plurality of shift registers is configured to output a driving signal through a corresponding one of the plurality of driving-signal output terminals of the gate driving circuit.

11. A display device, comprising:

the array substrate according to claim 1.

12. The display device according to claim 1, further comprising:

a detection device comprising at least one detection terminal, wherein the non-display region further comprises at least one connection terminal electrically connected with a second end of the at least one test line and each of the at least one connection terminal is configured to be electrically connected with one of the at least one detection terminal on the detection device.

13. The display device according to claim 12, wherein the detection circuit is a flexible circuit board or a printed circuit board.

14. The display device according to claim 13, wherein in case that the detection device is the printed circuit board, the display device further comprises a flexible circuit board configured to electrically connect the at least one connection terminal with the at least one detection terminal.

15. A method for detecting the array substrate according to claim 1, the method comprising:

short-circuiting at least one of the plurality of driving-signal traces to be detected and the at least one test line; and

electrically connecting a detection device with at least one connection terminal electrically connected to the at least one test line, and detecting a driving signal on the at least one test line.

16. The method according to claim 15, wherein after short-circuiting at least one of the plurality of driving-signal traces to be detected and the at least one test line, the method further comprises:

electrically disconnecting the short-circuited at least one of the plurality of driving-signal traces from at least one of the plurality of driving-signal output terminals in the gate driving circuit; and

inputting a corresponding driving signal to the disconnected at least one of the plurality of driving-signal traces through the at least one test line.

17. The method according to claim 15, wherein the short-circuiting at least one of the plurality of driving-signal traces to be detected and the at least one test line comprises:

welding the at least one of the plurality of driving-signal traces to be detected and the at least one test line at a position where the at least one of the plurality of driving-signal traces to be detected and the at least one test line overlap with each other by a laser so as to short-circuit the at least one of the plurality of the driving-signal traces to be detected and the at least one test line.

18. The method according to claim 16, wherein electrically disconnecting the short-circuited at least one of the plurality of driving-signal traces from at least one of the plurality of driving-signal output terminals in the gate driving circuit, comprises:

electrically disconnecting the short-circuited at least one of the plurality of driving-signal traces from at least one of the plurality of driving-signal output terminals of a plurality of shift registers cascaded to form a plurality of stages in the gate driving circuit, and each of the plurality of driving-signal output terminals corresponds to one of the plurality of shift registers.