SHIFT REGISTER UNIT, GATE DRIVING CIRCUIT AND DRIVING METHOD, AND DISPLAY APPARATUS

• US 20180108426A1
• Filed: 08/12/2016
• Published: 04/19/2018
• Est. Priority Date: 02/03/2016
• Status: Active Grant

• Current Assignee: BOE Technology Group Co., Ltd.
• Original Assignee: BOE Technology Group Co., Ltd.
• Inventors: Zheng, Haoliang, Han, Seungwoo, Yao, Xing, Choi, Hyunsic, Shang, Guangliang, Han, Mingfu, Im, Yunsik, JUN, Jungmok, Dong, Xue
• Granted Patent: US 10,002,675 B2
• Time in Patent Office: Days
• CPC Class Codes: G09G 2310/0267 Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G09G 3/3688 suitable for active matrices only
• CPC Class Codes: G11C 19/184 with field-effect transistors, e.g. MOS-FET
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence
• CPC Class Codes: H01L 27/1222 with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1251 comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs

Abstract

The present application discloses a method of driving a gate driving circuit in an operation cycle divided into a first sub-cycle and a second sub-cycle, including providing a gate driving circuit having a first plurality of shift register units with a second plurality of shift register units, the first plurality of shift register units being configured so that each odd/even numbered shift register unit includes a first bias-control terminal to receive a first/second bias signal CLK1/CLK2, a second bias-control terminal to receive a second/first bias signal CLK2/CLK1, and a first control level terminal provided with a first control voltage VC1, the second plurality of shift register units being configured so that each odd/even numbered shift register unit includes a third bias-control terminal to receive a third/fourth bias signal CLK3/CLK4, a fourth bias-control terminal to receive a fourth/third bias signal CLK4/CLK3, and a second control level terminal provided with a second control voltage VC2; configuring the first bias signal CLK1 and the second bias signal CLK2 as first pair of clock signals at respective turn-on level and turn-off level with inverted phase in the first sub-cycle; setting the first control voltage VC1 to a turn-off level so that the first plurality of shift register units is controlled along with the first pair of clock signals to respectively output corresponding gate driving output signals in an output phase within the first sub-cycle; setting both the third bias signal CLK3 and the fourth bias signal CLK4 to a turn-off level and the second control voltage VC2 to turn-on level during the first sub-cycle; configuring the third bias signal CLK3 and the fourth bias signal CLK4 as second pair of clock signals at respective turn-on level and turn-off level with inverted phase in the second sub-cycle; setting the second control voltage VC2 to a turn-off level so that the second plurality of shift register units are controlled along with the second pair of clock signals to respectively output corresponding gate driving output signals in an output phase within the second sub-cycle; and setting the first bias signal CLK1 and the second bias signal CLK2 to a turn-off level and the second control voltage VC1 to a turn-on level during the second sub-cycle.

Claims

1. A method of driving a gate driving circuit in an operation cycle divided into a first sub-cycle and a second sub-cycle, the method comprising:

providing a gate driving circuit having a first plurality of shift register units with a second plurality of shift register units, the first plurality of shift register units being configured so that each odd/even numbered shift register unit includes a first bias-control terminal to receive a first/second bias signal CLK1/CLK2, a second bias-control terminal to receive a second/first bias signal CLK2/CLK1, and a first control level terminal provided with a first control voltage VC1, the second plurality of shift register units being configured so that each odd/even numbered shift register unit includes a third bias-control terminal to receive a third/fourth bias signal CLK3/CLK4, a fourth bias-control terminal to receive a fourth/third bias signal CLK4/CLK3, and a second control level terminal provided with a second control voltage VC2;

configuring the first bias signal CLK1 and the second bias signal CLK2 as first pair of clock signals at respective turn-on level and turn-off level with inverted phase in the first sub-cycle;

setting the first control voltage VC1 to a turn-off level so that the first plurality of shift register units is controlled along with the first pair of clock signals to respectively output corresponding gate driving output signals in an output phase within the first sub-cycle;

setting both the third bias signal CLK3 and the fourth bias signal CLK4 to a turn-off level and the second control voltage VC2 to turn-on level during the first sub-cycle;

configuring the third bias signal CLK3 and the fourth bias signal CLK4 as second pair of clock signals at respective turn-on level and turn-off level with inverted phase in the second sub-cycle;

setting the second control voltage VC2 to a turn-off level so that the second plurality of shift register units are controlled along with the second pair of clock signals to respectively output corresponding gate driving output signals in an output phase within the second sub-cycle; and

setting the first bias signal CLK1 and the second bias signal CLK2 to a turn-off level and the second control voltage VC1 to a turn-on level during the second sub-cycle.

2. The method of claim 1, wherein the first plurality of shift register units comprises N shift register units cascaded in series from a first unit to Nth unit, N being a natural integer;

the second plurality of shift register units comprises M shift register units cascaded in series from (N+1)th unit to (N+M)th unit, M being a natural integer;

the Nth unit being cascaded in series with the (N+1)th unit; and

M equals to N.

3. The method of claim 2, wherein the first sub-cycle and the second sub-cycle comprise two equal time periods, each of the first sub-cycle and the second sub-cycle comprises an input phase, an output phase, a reset phase, and a reset-maintaining phase, the second/first sub-cycle is a reverse-bias phase associated with the first/second sub-cycle.

4. The method of claim 3, further comprising applying a third pair of clock signals with respective turn-on level and turn-off level at inverted phase to an output control terminal of respective odd and even numbered shift register units during both the first sub-cycle and the second sub-cycle.

5. The method of claim 2, wherein each shift register unit have a same circuit configuration as a (n)th unit, where n is a natural integer serial number of one of the first plurality of shift register units and the second plurality of shift register units, the (n)th unit comprising:

a first pull-up node control module having an input terminal and a reset terminal and being coupled to a pull-up node, the input terminal receiving a (n−

1)th gate driving output signal from an adjacent (n−

1)th unit for pulling up the pull-up node to a turn-on level during the input phase and bootstrapping the pull-up node above the turn-on level during the output phase, the reset terminal receiving a (n+1)th gate driving output signal from an adjacent (n+1)th unit for pulling down the pull-up node back to a turn-off level during the reset phase;

an output module coupled to the pull-up node and having an output terminal for outputting (n)th gate driving output signal at a turn-on level based on bootstrapping the pull-up node above the turn-on level during the output phase;

a first pull-down node control module coupled to the pull-up node and a pull-down node and receiving the (n−

1)th gate driving output signal from the first input terminal for pulling down the pull-down node to a turn-on level during the input phase when the pull-up node is at a turn-on level;

a second pull-up node control module coupled between the pull-up node and the pull-down node for pulling down the pull-up node to a turn-off level when the pull-down node is at a turn-on level;

a pull-down module coupled between the pull-down node and the output terminal for controlling the (n)th gate driving output signal at a turn-on level during the reset phase by controlling the pull-down node to a turn-on level, and keeping the (n)th gate driving output signal at a turn-off level during a reset-maintaining phase; and

a reverse-bias control module coupled to both the second pull-up node control module and the pull-down module.

6. The method of claim 5, wherein the reverse-bias control module comprises a first transistor having a source provided with a turn-off level, a drain coupled to the pull-down node, and a gate connected to the first/second control level terminal provided with the first/second control voltage VC1/VC2 if the reverse-bias control module belongs to one of the first/second plurality of shift register units.

7. The method of claim 5, wherein the second pull-up node control module comprises a second transistor having a gate connected to the pull-down node, a drain connected to the pull-up node, and a source connected to the first/second control level terminal provided with the first/second control voltage VC1/VC2 if the second pull-up node control module belongs to one of the first/second plurality of shift register units.

8. The method of claim 5, wherein the (n)th unit is an odd/even numbered shift register unit of the first plurality of shift register units, the pull-down module thereof comprises:

a third transistor having a drain connected to the pull-down node, a gate and a source commonly connected to the second/first bias-control terminal provided with the second/first bias signal CLK2/CLK1; and

a fourth transistor having a gate connected to the first/second bias-control terminal provided with the first/second bias signal CLK1/CLK2, a drain connected to the pull-down node, and a source connected to the first control level terminal; and

a fifth transistor having a gate connected to the pull-down node, a drain connected to the output terminal provided with the (n)th gate driving output signal, and a source connected to the first control level terminal provided with the first control voltage VC1.

9. The method of claim 5, wherein the (n)th unit is an odd/even numbered shift register unit of the second plurality of shift register units, the pull-down module thereof comprises:

a third transistor having a drain connected to the pull-down node, a gate and a source commonly connected to the fourth/third bias-control terminal provided with the fourth/third bias signal CLK4/CLK3;

a fourth transistor having a gate connected to the third/fourth bias-control terminal provided with the third/fourth bias signal CLK3/CLK4, a drain connected to the pull-down node, and a source connected to the second control level terminal provided with the second control voltage VC2; and

a fifth transistor having a gate connected to the pull-down node, a drain connected to the output terminal provided with the (n)th gate driving output signal, and a source connected to the second control level terminal provided with the second control voltage VC2.

10. The method of claim 5, further comprising using an output control module in the (n)th unit of the first/second plurality of shift register units to control outputting the (n)th gate driving output signal at a turn-off level during the second/first sub-cycle, wherein the output control module comprises a sixth transistor having a gate provided with to a clock signal, a drain connected to the output terminal, and a source provided with a turn-off level.

11. The method of claim 5, wherein the first pull-up node-control module comprises:

a seventh transistor having a gate and a source commonly connected to the input terminal, and a drain connected to the pull-up node;

an eighth transistor having a gate connected to the reset terminal, a drain connected to the pull-up node, and a source provided with a turn-off level; and

a storage capacitor having a first terminal connected to the pull-up node and a second terminal connected to the output terminal.

12. The method of claim 5, wherein the (n)th unit is an odd/even numbered shift register unit of the first plurality of shift register units, the output module thereof comprises a ninth transistor having a gate connected to the pull-up node, a source connected to the first/second bias-control terminal provided with the first/second bias signal CLK1/CLK2, and a drain connected to the output terminal.

13. The method of claim 5, wherein the (n)th unit is an odd/even numbered shift register unit of the second plurality of shift register units, the output module thereof comprises a ninth transistor having a gate connected to the pull-up node, a source connected to the third/fourth bias-control terminal provided with the third/fourth bias signal CLK3/CLK4, and a drain connected to the output terminal.

14. The method of claim 5, wherein the first pull-down node-control module comprises:

a tenth transistor having a gate connected to the pull-up node, a drain connected to the pull-down node, and a source provided with a turn-off level; and

an eleventh transistor having a gate controlled by the (n−

1)th gate driving output signal from the adjacent (n−

1)th unit, a drain connected to the pull-down node, and a source provided with a turn-off level.

15. The method of claim 5, further comprising:

a starting module connected to a start terminal and the pull-down node, the start terminal being provided with a starting signal at a turn-on level for controlling the pull-down node at a turn-on level;

a shift reset module connected to a shift reset terminal and the pull-up node, the shift reset terminal being provided with a shift reset signal at a turn-on level for controlling the pull-up node at a turn-off level; and

an output pull-down module for controlling the output terminal with the (n)th gate driving output signal at a turn-off level when the (n+1)th gate driving output signal is provided with a turn-on level at the reset terminal.

16. The method of claim 15, wherein the starting module comprises a twelfth transistor having a gate and a source commonly provided with the starting signal and a drain connected to the pull-down node;

the shift reset module comprises a thirteenth transistor having a gate controlled by the shift reset signal, a drain connected to the pull-up node, and a source provided with a turn-off level; and

the output pull-down module comprises a fourteenth transistor having a gate connected to the reset terminal provided with the (n+1)th gate driving output signal, a drain connected to the output terminal for outputting the (n)th gate driving output signal, and a source provided with a turn-off level.

17. The method of claim 15, wherein the (n)th unit is a first unit of the first plurality of shift register units, the first pull-up node control module thereof comprises an input terminal to receive the starting signal for pulling up the pull-up node to a turn-on level during the input phase and bootstrapping the pull-up node above the turn-on level during the output phase.

18. The method of claim 15, wherein the (n)th unit is a last unit of the second plurality of shift register units, the first pull-up node control module thereof comprises a reset terminal to receive the shift reset signal for pulling down the pull-up node back to a turn-off level during the reset phase.

19. The method of claim 5, wherein the reverse-bias control module of each of the first/second plurality of shift register units is used to set a reverse bias blocking state to each transistor in the second pull-up node control module and pull-down module thereof during the second/first sub-cycle.

20. A gate driving circuit, comprising a first plurality of shift register units cascaded in series and a second plurality of shift register units cascaded in series, each of the second plurality of shift register units except a last shift register unit has an output terminal outputting a gate driving output signal which is used as an input signal at an input terminal of a next adjacent shift register unit, and each of the first plurality of shift register units except a first shift register has an output terminal outputting a gate driving output signal which is used as a reset signal at a reset terminal of a previous adjacent shift register unit;

wherein the first plurality of shift register units being configured so that each odd/even numbered shift register unit includes a first bias-control terminal to receive a first/second bias signal, a second bias-control terminal to receive a second/first bias signal, and a first control level terminal provided with a first control voltage, the second plurality of shift register units being configured so that each odd/even numbered shift register unit includes a third bias-control terminal to receive a third/fourth bias signal, a fourth bias-control terminal to receive a fourth/third bias signal, and a second control level terminal provided with a second control voltage level; and

the first plurality of shift register units is configured to output respective gate driving output signals during a first sub-cycle while the second plurality of shift register units is partially configured to be in a reverse-bias state, and the first plurality of shift register units is partially configured to be in a reverse-bias state during a second sub-cycle while the second plurality of shift register units is configured t to output respective gate driving output signals, wherein the second sub-cycle sequentially follows the first sub-cycle plus to be one complete operation cycle.

21. (canceled)

22. (canceled)