SEMICONDUCTOR PACKAGE WITH THREE-DIMENSIONAL ANTENNA

• US 20180108624A1
• Filed: 12/14/2017
• Published: 04/19/2018
• Est. Priority Date: 01/06/2016
• Status: Active Grant

• Current Assignee: MediaTek, Inc.
• Original Assignee: MediaTek, Inc.
• Inventors: HSU, Chih-Chun, LIN, Sheng-Mou
• Granted Patent: US 10,340,235 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device antennas per se H01Q
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/1421 RF devices
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/3025 Electromagnetic shielding

Abstract

A semiconductor package is provided. The semiconductor package includes a package substrate having a first region and a second region defined between an edge of the package substrate and an edge of the first region, a semiconductor die disposed on the package substrate in the first region, a conductive shielding element disposed on the package substrate and covering the semiconductor die, and a three-dimensional (3D) antenna. The 3D antenna includes a planar structure portion disposed on the package substrate in the second region, and a bridge structure portion above the planar structure portion and connected thereto.

Claims

1. A semiconductor package, comprising:

a package substrate having a first region and a second region defined between an edge of the package substrate and an edge of the first region;

a semiconductor die disposed on the package substrate in the first region;

a conductive shielding element disposed on the package substrate and covering the semiconductor die; and

a three-dimensional (3D) antenna, comprising;

a planar structure portion disposed on the package substrate in the second region; and

a bridge structure portion above the planar structure portion and connected thereto.

2. The semiconductor package as claimed in claim 1, wherein the planar structure portion of the 3D antenna comprises a folded pattern and first and second bar patterns connected thereto.

3. The semiconductor package as claimed in claim 2, wherein the first bar pattern has an end in the first region to serve as a feeding point of the 3D antenna.

4. The semiconductor package as claimed in claim 2, wherein the second bar pattern is parallel to the first bar pattern and grounded via the package substrate.

5. The semiconductor package as claimed in claim 2, wherein the conductive shielding element has an opening in a sidewall thereof, such that the first bar pattern passes through the conductive shielding element via the opening.

6. The semiconductor package as claimed in claim 1, wherein the bridge structure of the 3D antenna has an end to serve as an open end of the 3D antenna.

7. A semiconductor package, comprising:

a package substrate having a first region and a second region defined between an edge of the package substrate and an edge of the first region;

a molding compound disposed on the package substrate in the first and second regions;

a semiconductor die disposed on the package substrate in the first region and inside the molding compound;

a three-dimensional (3D) antenna, comprising;

a planar structure portion on the package substrate in the second region; and

a wall structure portion contacting the planar structure portion and covering a top surface or one of sidewalls of the molding compound in the second region; and

a conductive shielding element disposed on the package substrate to cover the semiconductor die.

8. The semiconductor package as claimed in claim 7, wherein the planar structure portion of the 3D antenna comprises a spiral pattern and a bar pattern separated therefrom.

9. The semiconductor package as claimed in claim 8, wherein the bar pattern has one end in the first region to serve as a feeding point of the 3D antenna.

10. The semiconductor package as claimed in claim 8, wherein the spiral pattern has an end to serve as an open end of the 3D antenna.

11. The semiconductor package as claimed in claim 8, wherein a spacer portion of the conductive shielding element has an opening, such that the bar pattern passes through the spacer portion via the opening.

12. The semiconductor package as claimed in claim 8, wherein the 3D antenna further comprises first and second conductive vias that are disposed in the package substrate in the second region and exposed from the edge of the package substrate.

13. The semiconductor package as claimed in claim 12, wherein the first conductive via is electrically connected between the spiral pattern and the wall structure portion and the second conductive via is electrically connected between the bar pattern and the wall structure portion.

14. The semiconductor package as claimed in claim 7, wherein the conductive shielding element further comprises a plate portion covering a top surface of the molding compound in the first region, connected to the spacer portion, and separated from the wall structure portion of the 3D antenna.

15. A semiconductor package assembly, comprising:

a printed circuit board (PCB) having a keep-out region;

a package substrate disposed on the PCB, wherein the package substrate has a first region and a second region defined between an edge of the package substrate and an edge of the first region and corresponding to the keep-out region;

a semiconductor die disposed on the package substrate in the first region;

a conductive shielding element disposed on the package substrate and covering the semiconductor die;

a three-dimensional (3D) antenna, comprising;

a planar structure portion disposed on the package substrate in the second region; and

a bridge structure portion above the planar structure portion and connected thereto; and

a molding compound encapsulating the conductive shielding element and the 3D antenna.

16. The semiconductor package assembly as claimed in claim 15, wherein the planar structure portion of the 3D antenna comprises a folded pattern and first and second bar patterns connected thereto.

17. The semiconductor package assembly as claimed in claim 16, wherein the first bar pattern has an end in the first region to serve as a feeding point of the 3D antenna and the second bar pattern is parallel to the first bar pattern and grounded via the package substrate.

18. The semiconductor package assembly as claimed in claim 16, wherein the conductive shielding element has an opening in a sidewall thereof, such that the first bar pattern passes through the conductive shielding element via the opening.

19. The semiconductor package assembly as claimed in claim 15, wherein the keep-out region is located near an edge of the PCB.

20. A semiconductor package assembly, comprising:

a printed circuit board (PCB) having a keep-out region;

a package substrate disposed on the PCB, wherein the package substrate has a first region and a second region defined between an edge of the package substrate and an edge of the first region and corresponding to the keep-out region;

a molding compound disposed on the package substrate in the first and second regions;

a semiconductor die disposed on the package substrate in the first region and inside the molding compound;

a three-dimensional (3D) antenna, comprising;

a planar structure portion on the package substrate in the second region; and

a wall structure portion contacting the planar structure portion and covering a top surface or one of sidewalls of the molding compound in the second region; and

a conductive shielding element disposed on the package substrate to cover the semiconductor die.

21. The semiconductor package assembly as claimed in claim 20, wherein the planar structure portion of the 3D antenna comprises a spiral pattern and a bar pattern separated therefrom.

22. The semiconductor package assembly as claimed in claim 21, wherein the bar pattern has one end in the first region to serve as a feeding point of the 3D antenna and the spiral pattern has an end to serve as an open end of the 3D antenna.

23. The semiconductor package assembly as claimed in claim 21, wherein a spacer portion of the conductive shielding element has an opening, such that the bar pattern passes through the spacer portion via the opening.

24. The semiconductor package assembly as claimed in claim 21, wherein the 3D antenna further comprises first and second conductive vias that are disposed in the package substrate in the second region and exposed from the edge of the package substrate, and wherein the first conductive via is electrically connected between the spiral pattern and the wall structure portion and the second conductive via is electrically connected between the bar pattern and the wall structure portion.

25. The semiconductor package assembly as claimed in claim 20, wherein the conductive shielding element further comprises a plate portion covering a top surface of the molding compound in the first region, connected to the spacer portion, and separated from the wall structure portion of the 3D antenna.

26. The semiconductor package assembly as claimed in claim 20, wherein the keep-out region is located near an edge of the PCB.