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CONNECTING TECHNIQUES FOR STACKED CMOS DEVICES

  • US 20180108635A1
  • Filed: 12/19/2017
  • Published: 04/19/2018
  • Est. Priority Date: 12/11/2013
  • Status: Active Grant
First Claim
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1. An integrated circuit, comprising:

  • a semiconductor substrate;

    an inter-tier interconnecting structure disposed within the semiconductor substrate and comprising a first connection point at a lower surface of the inter-tier interconnecting structure and a second connection point at an upper surface of the inter-tier interconnecting structure, wherein the first connection point and the second connection point are not vertically aligned; and

    wherein the inter-tier interconnecting structure comprises one or more conductive layers extending between the first and second connection points.

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