CONNECTING TECHNIQUES FOR STACKED CMOS DEVICES

• US 20180108635A1
• Filed: 12/19/2017
• Published: 04/19/2018
• Est. Priority Date: 12/11/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Tseng, Hsiang-Jen, Chen, Wei-Yu, Chiang, Ting-Wei, Tien, Li-Chun
• Granted Patent: US 10,497,661 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 2027/11887 Three levels of metal
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06548 Conductive via connections through the substrate, container, or encapsulation
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/53223 Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53252 Additional layers associated with noble-metal layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53266 Additional layers associated with refractory-metal layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/535 : including internal interconnections, e.g. cross-under constructions internal lead connections H01L23/481
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/25 : of a plurality of high density interconnect connectors
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/074 : Stacked arrangements of non-apertured devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 27/0688 : Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a semiconductor substrate, and an inter-tier interconnecting structure disposed within the semiconductor substrate. The inter-tier interconnect structure includes a first connection point at a lower surface of the inter-tier interconnecting structure and a second connection point at an upper surface of the inter-tier interconnecting structure. The first connection point and the second connection point are not vertically aligned. The inter-tier interconnecting structure includes one or more conductive layers extending between the first and second connection points.

Claims

1. An integrated circuit, comprising:

a semiconductor substrate;

an inter-tier interconnecting structure disposed within the semiconductor substrate and comprising a first connection point at a lower surface of the inter-tier interconnecting structure and a second connection point at an upper surface of the inter-tier interconnecting structure, wherein the first connection point and the second connection point are not vertically aligned; and

wherein the inter-tier interconnecting structure comprises one or more conductive layers extending between the first and second connection points.

2. The integrated circuit of claim 1, wherein the inter-tier interconnecting structure comprises a first segment extending in a first direction and a second segment protruding outward from a sidewall of the first segment in a second direction substantially perpendicular to the first direction.

3. The integrated circuit of claim 1, wherein the inter-tier interconnecting structure comprises a first conductive layer and a second conductive layer having a different footprint than the first conductive layer.

4. The integrated circuit of claim 3, wherein the second conductive layer laterally extends past a sidewall of the first conductive layer.

5. The integrated circuit of claim 3, further comprising:

a semiconductor device arranged along a first side of the semiconductor substrate;

wherein sidewalls of the semiconductor substrate define a trench extending within the first side of the semiconductor substrate and comprising a rectangular shape; and

wherein the second conductive layer is disposed within the trench.

6. The integrated circuit of claim 3,

wherein the second conductive layer comprises a first segment contacting a first point along an upper surface of the first conductive layer and a non-continuous second segment contacting a second point along the upper surface of the first conductive layer;

and

wherein the first segment and the second segment are completely separated by the semiconductor substrate.

7. The integrated circuit of claim 1, wherein the inter-tier interconnecting structure comprises a “

T”

shape as viewed along a cross-section of the semiconductor substrate.

8. The integrated circuit of claim 1, wherein the inter-tier interconnecting structure extends from within the semiconductor substrate to a position that is below a bottommost surface of the semiconductor substrate.

9. An integrated circuit, comprising:

a semiconductor substrate; and

an inter-tier interconnecting structure disposed within the semiconductor substrate, wherein the inter-tier interconnecting structure comprises a first segment extending in a first direction and a second segment protruding outward from a sidewall of the first segment in a second direction that is substantially perpendicular to the first direction.

10. The integrated circuit of claim 9, wherein the inter-tier interconnecting structure comprises:

a first conductive layer disposed inside the semiconductor substrate; and

a second conductive layer disposed inside the semiconductor substrate over the first conductive layer and comprising the first segment extending in the first direction and the second segment protruding outward from the sidewall of the first segment.

11. The integrated circuit of claim 10, wherein the first conductive layer and the second conductive layer have different patterns as viewed from above the semiconductor substrate.

12. The integrated circuit of claim 10, further comprising:

a third conductive layer disposed inside the semiconductor substrate over the second conductive layer and having a different pattern than the first conductive layer and the second conductive layer as viewed from above the semiconductor substrate.

13. The integrated circuit of claim 10, wherein the second conductive layer has a bottommost surface that extends past the first conductive layer in the first direction and in the second direction.

14. The integrated circuit of claim 9, further comprising:

a semiconductor device arranged along a first side of the semiconductor substrate, wherein the inter-tier interconnecting structure comprises a rectangular upper surface extending along the first side of the semiconductor substrate.

15. The integrated circuit of claim 9, wherein the inter-tier interconnecting structure comprises an “

L”

shape as viewed from above the semiconductor substrate.

16. An integrated circuit, comprising:

a semiconductor substrate;

a first conductive layer disposed inside the semiconductor substrate and a second conductive layer disposed inside the semiconductor substrate over the first conductive layer; and

wherein the second conductive layer extends past a sidewall of the first conductive layer.

17. The integrated circuit of claim 16, wherein a first upper connection point is arranged along an upper surface of the second conductive layer and a second upper connection point is arranged along the upper surface of the second conductive layer at a location separated from the first connection point by a non-zero distance.

18. The integrated circuit of claim 16, further comprising:

a semiconductor device arranged along a first surface of the semiconductor substrate, wherein the second conductive layer extends along a trench within the first surface of the semiconductor substrate.

19. The integrated circuit of claim 18, further comprising:

a dielectric structure disposed on the first surface of the semiconductor substrate; and

a first plurality of conductive interconnect layers surrounded by the dielectric structure, wherein the first plurality of conductive interconnect layers are coupled to the second conductive layer.

20. The integrated circuit of claim 16, wherein the first conductive layer and the second conductive layer have different patterns as viewed from above the semiconductor substrate.