SEMICONDUCTOR DEVICE

• US 20180108737A1
• Filed: 10/13/2017
• Published: 04/19/2018
• Est. Priority Date: 10/14/2016
• Status: Active Grant

• Current Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Original Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Inventors: NAITO, Tatsuya
• Granted Patent: US 10,559,663 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 27/0716 in combination with vertical bipolar transistors and diodes, or capacitors, or resistors
• CPC Class Codes: H01L 27/0727 in combination with diodes, or capacitors or resistors
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0834 Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
• CPC Class Codes: H01L 29/1087 characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/32 the imperfections being within the semiconductor body
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/8613 Mesa PN junction diodes

Abstract

A semiconductor device is provided, including: a semiconductor substrate; a transistor section provided in the semiconductor substrate; and a diode section provided in the semiconductor substrate being adjacent to the transistor section, wherein the diode section includes: a second conductivity-type anode region; a first conductivity-type drift region; a first conductivity-type cathode region; a plurality of dummy trench portions arrayed along a predetermined array direction; a contact portion provided along an extending direction of the plurality of dummy trench portions that is different from the array direction; and a lower-surface side semiconductor region provided directly below a portion of the contact portion at an outer end in the extending direction.

Claims

1. A semiconductor device comprising:

a semiconductor substrate;

a transistor section provided in the semiconductor substrate; and

a diode section provided in the semiconductor substrate being adjacent to the transistor section;

wherein

the diode section comprises;

a second conductivity-type anode region at least partially exposed on an upper surface of the semiconductor substrate;

a first conductivity-type drift region provided below the anode region;

a first conductivity-type cathode region provided below the drift region;

a plurality of dummy trench portions that penetrate at least the anode region and are arrayed along a predetermined array direction;

a contact portion provided along an extending direction of the plurality of dummy trench portions that is different from the array direction; and

a second conductivity-type lower-surface side semiconductor region provided below the drift region and provided directly below an outer end portion of the contact portion in the extending direction.

2. The semiconductor device according to claim 1, wherein the transistor section comprises:

a first conductivity-type emitter region exposed on the upper surface of the semiconductor substrate;

a second conductivity-type base region at least partially provided below the emitter region;

a first conductivity-type drift region provided below the base region;

a plurality of gate trench portions that penetrate at least the base region and extend in the extending direction;

a first conductivity-type accumulation region having a higher first conductivity-type doping concentration than the drift region, provided between the base region and the drift region in the transistor section, and between the anode region and the drift region in the diode section; and

the lower-surface side semiconductor region provided below the drift region and also provided directly below a portion of the accumulation region in the diode section, the portion being at an outer end in the extending direction.

3. The semiconductor device according to claim 2, wherein:

an outer end portion of the accumulation region in the extending direction is provided on an inner side relative to an outer end portion of the contact portion in the extending direction; and

the lower-surface side semiconductor region is provided continuously at least from a position directly below an outer end portion of the contact portion in the extending direction to a position directly below an end portion of the accumulation region in the extending direction.

4. The semiconductor device according to claim 3, wherein a length from a portion of the lower-surface side semiconductor region at an end in the extending direction to a portion of the accumulation region at an outer end in the extending direction is greater than a length from a portion of the accumulation region at an outer end in the extending direction to a portion of the contact portion at an outer end in the extending direction.

5. The semiconductor device according to claim 3, wherein a length from a portion of the lower-surface side semiconductor region at an end in the extending direction to a portion of the accumulation region at an outer end in the extending direction is less than a length from a portion of the accumulation region at an outer end in the extending direction to a portion of the contact portion at an outer end in the extending direction.

6. The semiconductor device according to claim 2, wherein the lower-surface side semiconductor region is provided continuously to a position 200 μ

m or more inner from a portion of the accumulation region at an outer end in the extending direction.

7. The semiconductor device according to claim 2, wherein:

a portion of the accumulation region at an outer end in the extending direction is provided on an inner side relative to a portion of the contact portion at an outer end in the extending direction; and

the lower-surface side semiconductor region is provided continuously at least from a position directly below a portion of the contact portion at an outer end in the extending direction to a position at an outer side relative to a position directly below a portion of the accumulation region at an end in the extending direction.

8. The semiconductor device according to claim 2, wherein a region of the accumulation region at an end in the extending direction is provided such that a depth of the region at a more outer side is shallower.

9. The semiconductor device according to claim 1, wherein the diode section comprises, between the plurality of dummy trench portions, a high-concentration second conductivity-type region having a higher second conductivity-type doping concentration than the anode region and a high-concentration first conductivity-type region having a higher first conductivity-type doping concentration than the drift region.

10. The semiconductor device according to claim 9, wherein the high-concentration first conductivity-type region and the high-concentration second conductivity-type region extend in the extending direction and are adjacent to each other in the array direction.

11. The semiconductor device according to claim 9, wherein the high-concentration first conductivity-type region and the high-concentration second conductivity-type region extend in the array direction and are adjacent to each other in the extending direction.

12. The semiconductor device according to claim 1, wherein the transistor section comprises a plurality of gate trench portions, and

the plurality of gate trench portions comprise:

a first portion extending along the extending direction; and

a second portion which extends in the array direction and is connected to portions of a plurality of the first portions at an end in the extending direction.

13. The semiconductor device according to claim 12, wherein the second portion is connected to portions of three or more of the first portions at an end in the extending direction.

14. The semiconductor device according to claim 12, wherein the plurality of dummy trench portions in the diode section comprise:

a first portion extending along the extending direction; and

a second portion which extends in the array direction and is connected to portions of a plurality of the first portions at an end in extending direction.

15. The semiconductor device according to claim 14, wherein the second portion is connected to portions of three or more of the first portions at an end in the extending direction.

16. The semiconductor device according to claim 14, wherein the first portion of the plurality of gate trench portions and the first portion of the plurality of dummy trench portions are parallel to each other.

17. The semiconductor device according to claim 14, wherein the first portion of the plurality of gate trench portions and the first portion of the plurality of dummy trench portions are orthogonal to each other.

18. The semiconductor device according to claim 14, wherein the diode section comprises a lifetime killer region.

19. The semiconductor device according to claim 18, wherein the lifetime killer region extends to an outer side of the diode section relative to the first portion of the plurality of dummy trench portions.

20. The semiconductor device according to claim 18, wherein the lifetime killer region extends to an outer side of the diode section relative to the second portion of the plurality of dummy trench portions.

21. The semiconductor device according to claim 18, wherein the lifetime killer region extends to an outer side relative to the second portion of the plurality of gate trench portions.

22. The semiconductor device according to claim 20, wherein:

each of the plurality of gate trench portions comprises a gate conductive portion provided in contact with a gate insulating film and on an inner side of each of the plurality of gate trench portions relative to the gate insulating film;

the semiconductor device further comprises a gate metal layer which is provided outside the transistor section or the diode section in top view of the semiconductor substrate and is electrically connected to the gate conductive portion; and

the lifetime killer region extends outside the gate metal layer.

23. The semiconductor device according to claim 18, wherein a depth from the upper surface of the semiconductor substrate to the lifetime killer region is less than a depth from the lifetime killer region to a lower surface of the semiconductor substrate.