APPROACH TO MINIMIZATION OF STRAIN LOSS IN STRAINED FIN FIELD EFFECT TRANSISTORS
First Claim
Patent Images
1. A method of fabricating a vertical fin field effect transistor with a strained channel, comprising:
- forming a monolithic fin loop on a substrate;
forming a plurality of gate structures across straight portions of the monolithic fin loop;
forming a source/drain on the monolithic fin loop adjacent to each of the plurality of gate structures;
forming an interlevel dielectric on the monolithic fin loop; and
removing portions of the interlevel dielectric to form openings down to the each of the source/drains and substrate surface.
3 Assignments
0 Petitions
Accused Products
Abstract
A method of fabricating a vertical fin field effect transistor with a strained channel, including, forming a strained vertical fin on a substrate, forming a plurality of gate structures on the strained vertical fin, forming an interlevel dielectric on the strained vertical fin, forming a source/drain contact on the vertical fin adjacent to each of the plurality of gate structures, and selectively removing one or more of the source/drain contacts to form a trench adjacent to a gate structure.
15 Citations
20 Claims
-
1. A method of fabricating a vertical fin field effect transistor with a strained channel, comprising:
-
forming a monolithic fin loop on a substrate; forming a plurality of gate structures across straight portions of the monolithic fin loop; forming a source/drain on the monolithic fin loop adjacent to each of the plurality of gate structures; forming an interlevel dielectric on the monolithic fin loop; and removing portions of the interlevel dielectric to form openings down to the each of the source/drains and substrate surface. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
-
-
10. A method of fabricating a vertical fin field effect transistor with a strained channel, comprising:
-
forming a strained silicon-germanium (SiGe) vertical fin on a single crystal silicon substrate or a strained silicon (Si) vertical fin on a single crystal silicon-germanium substrate; forming three or more gate structures on the strained SiGe or Si vertical fin; forming a gate spacer on each of the three or more gate structures; forming an interlevel dielectric on the gate spacers; forming four or more openings in the interlevel dielectric; forming four or more source/drain contacts in the interlevel dielectric on the vertical fin, where at least two of the source/drain contacts are between the gate spacers; and selectively removing one or more of the source/drain contacts to form a trench in the interlevel dielectric. - View Dependent Claims (11, 12, 13, 14, 15)
-
-
16. A method of forming a vertical fin device, comprising:
-
forming a plurality of adjacent strained, straight, vertical fin segments on a substrate; forming a gate spacer on each of the plurality of strained, straight, vertical fin segments; forming a gate structure within each of the gate spacers; forming a source/drain contact on one or more of the plurality of strained, straight, vertical fin segments adjacent to at least one of the plurality of gate spacers; and forming an interlevel dielectric on each gate spacer and the source/drain contacts. - View Dependent Claims (17, 18, 19, 20)
-
Specification