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AUTOMATIC DETECTION OF CHANGE IN PLL LOCKING TREND

  • US 20180109370A1
  • Filed: 12/18/2017
  • Published: 04/19/2018
  • Est. Priority Date: 04/21/2016
  • Status: Active Grant
First Claim
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1. A phase lock loop (PLL), comprising:

  • a phase frequency detector (PFD) configured to compare a first frequency of a first time-varying signal and a second frequency of a second time-varying signal to provide a frequency error component of an error signal in a first mode of operation and in a second mode of operation;

    a time-to-digital converter (TDC) configured to compare a first phase of the first time-varying signal and a second phase of the second time-varying signal to provide a phase error component of the error signal in the second mode of operation;

    a digital controlled oscillator (DCO) configured to adjust the second frequency and the second phase based upon the error signal; and

    a controller configured to;

    compare a trend of the error signal to a previous trend of the error signal to detect for a change in the trend of the error signal, andinitiate a change in a mode of operation of the PLL from the first mode of operation to the second mode of operation or from the second mode of operation to the first mode of operation upon detecting the change in the trend of the error signal.

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