AUTOMATIC DETECTION OF CHANGE IN PLL LOCKING TREND

• US 20180109370A1
• Filed: 12/18/2017
• Published: 04/19/2018
• Est. Priority Date: 04/21/2016
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: TSAI, Tsung-Hsien, CHANG, Chih-Hsien
• Granted Patent: US 10,090,994 B2
• Time in Patent Office: Days
• CPC Class Codes: H03L 2207/50 All digital phase-locked loop
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/0994 comprising an accumulator
• CPC Class Codes: H04L 7/0331 with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence

Abstract

A phase lock loop (PLL), such as an all digital phase lock loop (ADPLL) to provide an example, of the present disclosure operates in a frequency tracking mode to adjust a frequency of the output signal to be proportional to a frequency of a reference input signal, or, in a phase tracking mode to adjust a phase of the output signal to match any variations in the reference input signal. The ADPLL includes a phase and/or frequency detector that provides an error signal representing a difference, in frequency and/or phase, between the output signal and the reference input signal. The ADPLL monitors a trend of the error signal, such as a positive trend, a negative trend, or a flat trend to provide some examples, and switches among the frequency tracking mode and the phase tracking mode upon detecting a change in the trend of the error signal.

Claims

1. A phase lock loop (PLL), comprising:

a phase frequency detector (PFD) configured to compare a first frequency of a first time-varying signal and a second frequency of a second time-varying signal to provide a frequency error component of an error signal in a first mode of operation and in a second mode of operation;

a time-to-digital converter (TDC) configured to compare a first phase of the first time-varying signal and a second phase of the second time-varying signal to provide a phase error component of the error signal in the second mode of operation;

a digital controlled oscillator (DCO) configured to adjust the second frequency and the second phase based upon the error signal; and

a controller configured to;

compare a trend of the error signal to a previous trend of the error signal to detect for a change in the trend of the error signal, and

initiate a change in a mode of operation of the PLL from the first mode of operation to the second mode of operation or from the second mode of operation to the first mode of operation upon detecting the change in the trend of the error signal.

2. The PLL of claim 1, wherein the TDC is further configured to be enabled in the first mode of operation and to be disabled in the second mode of operation.

3. The PLL of claim 1, wherein the trend comprises:

a positive trend;

a negative trend;

or

a flat trend.

4. The PLL of claim 1, wherein the first time-varying signal comprises an output signal of the PLL.

5. The PLL of claim 1, wherein the second time-varying signal comprises an input signal of the PLL.

6. A method for operating phase lock loop (PLL), the method comprising:

comparing, in a first mode of operation, a first frequency of a first time-varying signal and a second frequency of a second time-varying signal to provide a frequency error component of an error signal;

comparing, in a second mode of operation, the first frequency of the first time-varying signal and the second frequency of the second time-varying signal to provide the frequency error component of the error signal and a first phase of the first time-varying signal and a second phase of the second time-varying signal to provide a phase error component of the error signal in the second mode of operation;

adjusting the second frequency and the second phase based upon the error signal;

comparing a trend of an error signal to a previous trend of the error signal to detect for a change in the trend of the error signal; and

initiating a change in a mode of operation of the PLL from the first mode of operation to the second mode of operation or from the second mode of operation to the first mode of operation upon detecting the change in the trend of the error signal.

7. The method of claim 6, wherein the first and second modes of operation respectively comprise enabling and disabling the TDC.

8. The method of claim 6, wherein the trend comprises:

a positive trend;

a negative trend;

or

a flat trend.

9. The method of claim 6, wherein the first time-varying signal comprises an output signal of the PLL.

10. The method of claim 6, wherein the second time-varying signal comprises an input signal of the PLL.

11. A controller for controlling a phase lock loop (PLL), the controller comprising:

means for generating a clock signal based on an error signal, the error signal representing a difference between a frequency or a phase of a reference input signal of the PLL and a frequency or a phase of an output signal of the PLL;

means for sampling the error signal in accordance with the clock signal;

means for determining a trend of the sampled error signal;

means for comparing the trend of the sampled error signal to a previous trend of the sampled error signal to detect for a change in the trend of the sampled error signal; and

means for initiating a change in a mode of operation of the PLL upon detecting the change in the trend of the sampled error signal.

12. The controller of claim 11, wherein the trend of the sampled error signal comprises:

a positive trend;

a negative trend;

or

a flat trend.

13. The controller of claim 11, wherein the PLL comprises:

an all digital PLL (ADPLL).

14. The controller of claim 11, wherein the reference input signal and the output signal comprise a digital reference input signal and a digital output signal, respectively.

15. The controller of claim 11, wherein the reference input signal represents a digital representation of a first time-varying signal having a first frequency and a first phase, wherein the output signal represents a digital representation of a second time-varying signal having a second frequency and a second phase

16. The controller of claim 15, further comprising:

means for adjusting the second frequency to be proportional to the first frequency in a frequency tracking mode of operation.

17. The controller of claim 16, further comprising:

means for changing to a phase tracking mode of operation in response to the change in the mode of operation of the PLL to adjust the second phase to be proportional to the first phase.

18. The controller of claim 11, wherein the means for sampling the error signal samples the error signal to provide a plurality of samples of the error signal, and compares a first sample from among the plurality of samples and a second sample from among the plurality of samples to determine a second trend of the sampled error signal.

19. The controller of claim 18, wherein the means for initiating the change in the mode of operation of the PLL initiates the change in the mode of operation of the PLL when the trend of the sampled error signal differs from the second trend of the sampled error signal.

20. The controller of claim 18, wherein the means for initiating the change in the mode of operation of the PLL does not initiate the change in the mode of operation of the PLL when the trend of the sampled error signal is similar to the second trend of the sampled error signal.