THROUGH SILICON VIA (TSV) FORMATION IN INTEGRATED CIRCUITS

• US 20180111823A1
• Filed: 10/26/2016
• Published: 04/26/2018
• Est. Priority Date: 10/26/2016
• Status: Active Grant

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Nunan, Thomas Kieran, Chen, Li
• Granted Patent: US 11,097,942 B2
• Time in Patent Office: Days
• CPC Class Codes: B81B 2201/0228 Inertial sensors
• CPC Class Codes: B81B 2201/0235 Accelerometers
• CPC Class Codes: B81B 2201/0242 Gyroscopes
• CPC Class Codes: B81B 2201/0264 Pressure sensors
• CPC Class Codes: B81B 2203/0315 Cavities
• CPC Class Codes: B81B 2207/012 the micromechanical device and the control or processing electronics being separate parts in the same package
• CPC Class Codes: B81B 2207/07 Interconnects
• CPC Class Codes: B81B 2207/096 through the substrate
• CPC Class Codes: B81B 7/0006 Interconnects
• CPC Class Codes: B81C 1/00238 Joining a substrate with an electronic processing unit and a substrate with a micromechanical structure
• CPC Class Codes: B81C 2203/036 Fusion bonding
• CPC Class Codes: B81C 2203/037 Thermal bonding techniques not provided for in B81C2203/035 - B81C2203/036
• CPC Class Codes: B81C 2203/0792 Forming interconnections between the electronic processing unit and the micromechanical structure
• CPC Class Codes: B81C 3/001 Bonding of two components
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/1403 Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/14181 On opposite sides of the body
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures

Abstract

Integrated circuit substrates having through silicon vias (TSVs) are described. The TSVs are vias extending through the silicon substrate in which the integrated circuitry is formed. The TSVs may be formed prior to formation of the integrated circuitry on the integrated circuit substrate, allowing the use of via materials which can be fabricated at relatively small sizes. The integrated circuit substrates may be bonded with a substrate having a microelectromechanical systems (MEMS) device. In some such situations, the circuitry of the integrated circuit substrate may face away from the MEMS substrate since the TSVs may provide electrical connection from the circuitry side of the integrated circuit substrate to the MEMS device.

Claims

1. An apparatus, comprising:

a microelectromechanical systems (MEMS) substrate including a MEMS device;

an application specific integrated circuit (ASIC) substrate having a device surface, a backside opposite the device surface, an ASIC on the device surface, and a through silicon via (TSV) connecting the device surface to the backside, wherein the TSV is formed of conductive polysilicon; and

wherein the MEMS substrate and ASIC substrate are bonded at the backside of the ASIC substrate such that the device surface is distal the MEMS substrate.

3. The apparatus of claim 1, wherein the TSV has an aspect ratio between 12:

1 and 30;

1.

4. The apparatus of claim 1, wherein the MEMS substrate and ASIC substrate define a sealed cavity between them in which MEMS device is disposed.

5. The apparatus of claim 4, wherein the MEMS device is an inertial sensor.

6. The apparatus of claim 1, wherein the MEMS substrate is a MEMS wafer having multiple instances of the MEMS device, wherein the ASIC substrate is an ASIC wafer having multiple instances of the ASIC, and wherein the MEMS wafer and ASIC are bonded together.

7. The apparatus of claim 1, wherein the TSV is connected to electrical circuitry on the MEMS substrate.

21. The apparatus of claim 1, wherein the MEMS device is an inertial sensor.

2. (canceled)

8. A method of forming a device including an application specific integrated circuit (ASIC), the method comprising:

forming a through silicon via (TSV) in a substrate prior to forming any metal features on the substrate; and

subsequent to forming the TSV in the substrate, forming ASIC components in a device surface of the substrate.

9. The method of claim 8, wherein forming the TSV in the substrate involves forming the TSV in the substrate prior to forming any of the ASIC components in the device surface of the substrate.

10. The method of claim 8, wherein forming the TSV in the substrate comprises forming a conductive path through at least part of the substrate.

11. The method of claim 8, wherein forming the TSV in the substrate comprises forming the TSV of conductive polysilicon.

12. The method of claim 8, wherein forming the TSV in the substrate comprises forming a conductive portion of the TSV at a first temperature, and wherein forming the ASIC components in the device surface is performed at a second temperature lower than the first temperature.

13. The method of claim 12, wherein forming the conductive portion of the TSV at a first temperature comprises performing an anneal of the TSV at the first temperature.

14. The method of claim 8, further comprising bonding the substrate comprising the TSV with a substrate comprising a MEMS device in an orientation such that the device surface faces away from the substrate comprising the MEMS device.

15. The method of claim 14, wherein bonding the substrate comprising the TSV with the substrate comprising the MEMS device comprises forming a sealed cavity in which the MEMS device is disposed.

16. A method of forming a device including an application specific integrated circuit, the method comprising:

forming a through silicon via (TSV) in a substrate using at least one processing step at a first temperature greater than 450°

C.; and

forming transistors of the application specific integrated circuit using temperatures less than the first temperature.

17. The method of claim 16, wherein forming the through silicon via comprises forming a doped polysilicon TSV.

18. The method of claim 16, wherein the at least one processing step comprises an anneal.

19. The method of claim 16, further comprising bonding the substrate comprising the TSV to a substrate comprising a microelectromechanical systems (MEMS) device.

20. The method of claim 19, wherein bonding the substrate comprising the TSV to a substrate comprising a microelectromechanical systems (MEMS) device comprises creating a sealed cavity in which the MEMS device is disposed, and wherein a surface of the substrate comprising the TSV in which the transistors are formed faces away from the substrate comprising the MEMS device.