DYNAMIC VARIABLE PRECISION COMPUTATION

• US 20180113678A1
• Filed: 10/20/2016
• Published: 04/26/2018
• Est. Priority Date: 10/20/2016
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Sadowski, Greg, Burleson, Wayne
• Granted Patent: US 10,296,292 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 7/4824 using signed-digit representation
• CPC Class Codes: G06F 7/729 using representation by a residue number system

Abstract

A conversion unit converts operands from a conventional number system that represents each binary number in the operands as one bit to redundant number system (RNS) operands that represent each binary number as a plurality of bits. An arithmetic logic unit performs an arithmetic operation on the RNS operands in a direction from a most significant bit (MSB) to a least significant bit (LSB). The arithmetic logic unit stops performing the arithmetic operation prior to performing the arithmetic operation on a target binary number indicated by a dynamic precision associated with the RNS operands. In some cases, a power supply provides power to bit slices in the arithmetic logic unit and a clock signal generator provides clock signals to the bit slices. Gate logic is configured to gate the power or the clock signals provided to a subset of the bit slices.

Claims

1. An apparatus comprising:

a conversion unit to convert operands from a conventional number system that represents each binary number in the operands as one bit to redundant number system (RNS) operands that represent each binary number as a plurality of bits; and

an arithmetic logic unit to perform an arithmetic operation on the RNS operands in a direction from a most significant bit (MSB) to a least significant bit (LSB) and to stop the arithmetic operation prior to performing the arithmetic operation on a target binary number indicated by a dynamic precision associated with the RNS operands.

2. The apparatus of claim 1, wherein the arithmetic logic unit further comprises:

a plurality of bit slices, each bit slice being configured to perform the arithmetic operation on one of the binary numbers in the RNS operands.

3. The apparatus of claim 2, wherein a carry-in bit received by a bit slice that operates on a more significant binary number from a bit slice that operates on a less significant binary number does not determine a value of a carry-out bit generated by the bit slice that operates on the more significant binary number.

4. The apparatus of claim 2, further comprising:

a control unit configured to provide enable signals to turn on a first subset of the plurality of bit slices, wherein the first subset operates on binary numbers in the RNS operands that are more significant than the target binary number.

5. The apparatus of claim 4, wherein the control unit is configured to determine the dynamic precision at runtime based on at least one of a data type of the RNS operands, a statistical representation of binary numbers in the RNS operands, or in response to at least one of changes in a battery level, or changes in a target accuracy of a result of the arithmetic operation.

6. The apparatus of claim 4, wherein the arithmetic logic unit is configured to receive accumulated errors associated with the RNS operands, and wherein the control unit is configured to modify the dynamic precision at runtime based on the accumulated errors.

7. The apparatus of claim 4, wherein the control unit does not provide enable signals to a second subset of the plurality of bit slices that operate on binary numbers in the RNS operands that are equal to or less significant than the target binary number.

8. The apparatus of claim 7, further comprising:

a power supply to provide power to the plurality of bit slices;

a clock signal generator to provide clock signals to the plurality of bit slices; and

gate logic configured to gate at least one of the power or the clock signals provided to the second subset.

9. The apparatus of claim 1, wherein the conversion unit is configured to selectively convert the operands from the conventional number system to the RNS operands based on a comparison of overhead required to perform the conversion and expected power savings produced by stopping the arithmetic operation prior to performing the arithmetic operation on the target binary number indicated by the dynamic precision associated with the RNS operands.

10. A method comprising:

converting operands from a conventional number system that represents each binary number in the operands as one bit to redundant number system (RNS) operands that represent each binary number as a plurality of bits;

performing an arithmetic operation on the RNS operands in a direction from a most significant bit (MSB) to a least significant bit (LSB); and

stopping the arithmetic operation prior to performing the arithmetic operation on a target binary number indicated by a dynamic precision associated with the RNS operands.

11. The method of claim 10, wherein performing the arithmetic operation on the RNS operands comprises independently performing the arithmetic operation on a plurality of binary numbers in the RNS operands using a plurality of bit slices implemented by an arithmetic logic unit, each bit slice being configured to perform the arithmetic operation on one of the binary numbers in the RNS operands.

12. The method of claim 11, wherein performing the arithmetic operation using the plurality of bit slices further comprises:

receiving a carry-in bit at a bit slice that operates on a more significant binary number from a bit slice that operates on a less significant binary number; and

providing a carry-out bit from the bit slice that operates on the more significant binary number, wherein the carry-in bit does not determine a value of the carry-out bit.

13. The method of claim 11, further comprising:

providing enable signals to turn on a first subset of the plurality of bit slices, wherein the first subset operates on binary numbers in the RNS operands that are more significant than the target binary number.

14. The method of claim 11, further comprising:

bypassing provision of enable signals to a second subset of the plurality of bit slices that operate on binary numbers in the RNS operands that are equal to or less significant than the target binary number.

15. The method of claim 14, further comprising:

gating at least one of power or clock signals provided to the second subset.

16. The method of claim 10, further comprising:

determining the dynamic precision at runtime based on at least one of a data type of the RNS operands, a statistical representation of binary numbers in the RNS operands, or in response to at least one of changes in a battery level, or changes in a target accuracy of a result of the arithmetic operation.

17. The method of claim 10, further comprising:

receiving accumulated errors associated with the RNS operands; and

modifying the dynamic precision at runtime based on the accumulated errors.

18. The method of claim 10, wherein converting the operands from the conventional number system to the RNS operands comprises converting the operands from the conventional number system to the RNS operands based on a comparison of overhead required to perform the conversion and expected power savings produced by stopping the arithmetic operation prior to performing the arithmetic operation on the target binary number indicated by the dynamic precision associated with the RNS operands.

19. An apparatus comprising:

a first conversion unit to convert operands from a conventional number system that represents each binary number in the operands as one bit to redundant number system (RNS) operands that represent each binary number as a plurality of bits;

an arithmetic logic unit to perform a sequence of arithmetic operations, wherein each of the arithmetic operations are performed on the RNS operands in a direction from a most significant bit (MSB) to a least significant bit (LSB), and wherein the arithmetic operations are stopped prior to performing the arithmetic operation on different target binary numbers indicated by different dynamic precisions associated with the arithmetic operations; and

a second conversion unit to convert RNS results of the sequence of arithmetic operations to the conventional number system.

20. The apparatus of claim 19, wherein converting the operands from the conventional number system to the RNS operands comprises converting the operands from the conventional number system to the RNS operands based on a comparison of overhead required to perform the conversion and expected power savings produced by stopping the arithmetic operations prior to performing the arithmetic operations on different target binary numbers indicated by different dynamic precisions associated with the arithmetic operations.