SEQUENCE AND TIMING CONTROL OF WRITING AND REWRITING PIXEL MEMORIES WITH SUBSTANTIALLY LOWER DATA RATE

• US 20180114477A1
• Filed: 09/25/2016
• Published: 04/26/2018
• Est. Priority Date: 09/25/2016
• Status: Active Application

• Current Assignee: Ishii, Fusao
• Original Assignee: Ishii, Fusao
• Inventors: Ishii, Fusao
• Application Number:
  US15/275,405
• Publication Number:
  US 20180114477A1
• Time in Patent Office: Days
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 2360/00 Aspects of the architecture of display systems
• CPC Class Codes: G09G 3/2014 by modulation of the duration of a single pulse during which the logic level remains constant
• CPC Class Codes: G09G 5/06 using colour palettes, e.g. look-up tables
• CPC Class Codes: G09G 5/10 Intensity circuits

Abstract

A Display system driven with binary pulse-width-modulation requires very high data transfer rate to achieve high grayscale. This invention discloses the embodiments of hardware structures and configurations which enable to reduce substantially the data transfer rate using non-sequential order of binary bits, wherein the combination of the sequences of binary bits is selected from the combinations which avoid simultaneous writing of multiple rows. The implementation of this invention substantially reduces the power consumption and the number of connecting pads of display chip

Claims

1. An image display system having a plurality of pixel elements to receive and apply digital image data of multiple bits to display image according to the digital image data, the image display system further comprising:

a controller to control a process of writing the digital image data into each of the pixel elements by dividing the image data of multiple bits into a plurality of groups and writing each group of bits into the pixel element in a non-sequential order that is unrelated to a significance order of bit, neither in an order of from a most significant bit (MSB) to a least significant bit (LSB) nor from the LSB to the MSB, and without a writing conflict in writing said memory data into two pixel elements simultaneously during a process of writing and a look up table containing at least one set of sequences of data writing for said display system.

2. The image display system of claim 1 wherein:

said look up table comprises look-up data stored in a non-volatile memory.

3. The image display system of claim 2 wherein:

said look up table is separate from display device

4. The image display system of claim 1 wherein:

said look up table is embedded inside display device

5. The image display system of claim 1 wherein:

the display controller and look-up-table are included as an integrated part of the display device

6. The image display system of claim 1 wherein:

the pixel elements in each of the rows are divided into groups including interleaved lines

7. An image display system having a plurality of pixel elements to receive and apply digital image data of multiple bits to display image according to the image data, the image display system further comprising:

a controller to control a process of writing the image data into each of the pixel elements by dividing the image data of multiple bits into groups and writing each group of bits into the pixel element in a non-sequential order of significance of bit, neither in an order of from a most significant bit (MSB) to a least significant bit (LSB) nor from the LSB to the MSB, and without a writing conflict in writing said memory data into two pixel elements simultaneously during the process of writing and high significance bits including MSB are subdivided into at least two units.

8. The image display system of claim 7 wherein:

a look up table containing data defining at least one set of sequences of writing the image data for said display.

9. The image display system of claim 7 wherein:

the pixel elements in each of the rows are divided into groups including interleaved lines.

10. An image display system having a plurality of pixel elements to receive and apply digital image data of multiple bits to display image according to the image data, the image display system further comprising:

a controller to control a process of writing the image data into each of the pixel elements by dividing the image data of multiple bits into groups and writing each group of bits into the pixel element in a non-sequential order of significance of bit, neither in an order of from a most significant bit (MSB) to a least significant bit (LSB) nor from the LSB to the MSB, and without a writing conflict in writing said memory data into two pixel elements simultaneously during the process of writing; and

said controller is made of FPGA.