CIRCUIT METHODOLOGY FOR HIGHLY LINEAR AND SYMMETRIC RESISTIVE PROCESSING UNIT

• US 20180114572A1
• Filed: 12/04/2017
• Published: 04/26/2018
• Est. Priority Date: 10/26/2016
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Gokmen, Tayfun, Kim, Seyoung, Lee, Hyung-Min, Lee, Wooram, Solomon, Paul Michael
• Granted Patent: US 10,269,425 B2
• Time in Patent Office: Days
• CPC Class Codes: G06N 3/02 Neural networks
• CPC Class Codes: G06N 3/049 Temporal neural networks, e.g. delay elements, oscillating neurons or pulsed inputs
• CPC Class Codes: G06N 3/065 Analogue means
• CPC Class Codes: G06N 3/084 Backpropagation, e.g. using gradient descent
• CPC Class Codes: G06N 3/088 Non-supervised learning, e.g. competitive learning
• CPC Class Codes: G11C 11/54 using elements simulating biological cells, e.g. neuron
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0038 Power supply circuits
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2213/77 Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

A processing unit includes a circuit including a current mirror, and a capacitor providing a weight based on a charge level of the capacitor. The capacitor is charged or discharged by the current mirror.

Claims

1. A processing unit, comprising:

a circuit including;

a current mirror; and

a capacitor providing a weight based on a charge level of the capacitor,

wherein the capacitor is charged or discharged by the current mirror.

2. The processing unit according to claim 1, further comprising a read out transistor connected to the capacitor,

wherein a stored voltage of the capacitor is read out to a gate of an output transistor by the read out transistor.

3. The processing unit according to claim 2, wherein the output transistor translates the capacitor'"'"'s voltage to a resistance.

4. The processing unit according to claim 2, wherein the read out transistor converts the voltage at the capacitor to resistance which is accessible from a source-drain terminals of the read out transistor by applying a read voltage.

5. The processing unit according to claim 1, wherein the bias voltages to a gate terminal of the current mirror transistors are supplied from and external circuit and also used as a global signal of programming mode for an array of the processing units.

6. The processing unit according to claim 1, wherein the read out transistor and current mirror each comprise a complementary-metal-oxide-semiconductor (CMOS) transistor.

7. An array of processing units comprising a plurality of the processing units according to claim 1.

8. The array of processing units according to claim 7, wherein the plurality of the processing units are configured in a cross-point array to train a neural network.

9. A method of a processing unit, the method comprising:

charging or discharging a capacitor of the processing unit by one of at least two current mirrors; and

providing a weight based on a charge level of the capacitor charged by the one of the at least two current mirrors.

10. The method according to claim 9, further comprising reading out a stored voltage of the capacitor to a gate of an output transistor by a read out transistor connected to the capacitor.

11. The method according to claim 10, further comprising of translating, by the output transistor, a voltage of the capacitor to a resistance value.

12. The method according to claim 9, further comprising of converting, by a read out transistor connected to the capacitor, the voltage at the capacitor to resistance accessible from source-drain terminals of the read out transistor by applying a read voltage.

13. The method according to claim 9, further comprising of supplying bias voltages to a gate terminal of the current mirror transistors from and external circuit and also using the bias voltages as a global signal of programming mode for a plurality of the processing units configured in an array.

14. The method according to claim 9, wherein the read out transistor and current mirrors each comprise a complementary-metal-oxide-semiconductor (CMOS) transistor.

15. The method according to claim 9, wherein a plurality of the processing units are configured as a cross-point array to train a neural network.

16. An array of processing units, each processing unit comprising:

a circuit including;

at least two current mirrors; and

a capacitor providing a weight based on a charge level of the capacitor,

wherein the capacitor is charged or discharged by one of the at least two current mirrors.

17. The array of processing units according to claim 16, further comprising a read out transistor connected to the capacitor,

wherein a stored voltage of the capacitor is read out to a gate of an output transistor by the read out transistor.

18. The array of processing units according to claim 17, wherein the output transistor translates the capacitor'"'"'s voltage to a resistance.

19. The array of processing units according to claim 18, wherein the read out transistor converts the voltage at the capacitor to resistance which is accessible from source-drain terminal by applying a read voltage, and

wherein the read out transistor and current mirrors each comprise a complementary-metal-oxide-semiconductor (CMOS) transistor.

20. The array of processing units according to claim 16, wherein bias voltages to a gate terminal of the current mirror transistors are supplied from and external circuit and also used as a global signal of programming mode for each of the processing units, and

wherein each of the processing units comprise a resistive processing unit (RPU).