Semiconductor Device

• US 20180114829A1
• Filed: 09/11/2017
• Published: 04/26/2018
• Est. Priority Date: 10/20/2016
• Status: Abandoned Application

• Current Assignee: Toyota Jidosha Kabushiki Kaisha (Toyota Motor Corporation)
• Original Assignee: Toyota Jidosha Kabushiki Kaisha (Toyota Motor Corporation)
• Inventors: NAGAOKA, Tatsuji, WATANABE, Yukihiko, URAKAMI, Yasushi
• Application Number:
  US15/700,919
• Publication Number:
  US 20180114829A1
• Time in Patent Office: Days
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/063 Reduced surface field [RESURF] pn-junction structures
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/7804 the other device being a pn-junction diode
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/872 Schottky diodes

Abstract

A semiconductor device includes a semiconductor substrate configured such that a trench is provided on a surface of the semiconductor substrate at a position of at least one of a boundary region disposed between a field-effect transistor region and a diode region, a boundary region disposed between the diode region and a peripheral voltage withstanding region, and a boundary region disposed between the field-effect transistor region and the peripheral voltage withstanding region; an insulating film covering an inner surface of the trench; and an electrode film covering an inner surface of the insulating film, the electrode film being configured to be electrically connected to one of a source electrode and an anode electrode.

Claims

1. A semiconductor device comprising:

a semiconductor substrate configured such that a trench is provided on a surface of the semiconductor substrate at a position of at least one of a boundary region disposed between a field-effect transistor region and a diode region, a boundary region disposed between the diode region and a peripheral voltage withstanding region, and a boundary region disposed between the field-effect transistor region and the peripheral voltage withstanding region;

an insulating film covering an inner surface of the trench; and

an electrode film covering an inner surface of the insulating film, the electrode film being configured to be electrically connected to one of a source electrode and an anode electrode.

2. The semiconductor device according to claim 1, wherein:

a p-type region is provided in an adjacent region adjacent to the boundary region; and

a bottom surface of the electrode film is disposed at a position deeper than a bottom surface of the p-type region.

3. The semiconductor device according to claim 2, wherein the p-type region provided in the adjacent region reaches a side surface of the trench.

4. The semiconductor device according to claim 1, wherein:

a trench gate electrode is provided in an adjacent region adjacent to the boundary region; and

a bottom surface of the electrode film is disposed at a position deeper than a bottom surface of the trench gate electrode.

5. The semiconductor device according to claim 1, wherein:

an n-type impurity low concentration region having an impurity concentration lower than that of an n-type drift layer is provided in the boundary region; and

the trench is provided in the n-type impurity low concentration region.

6. The semiconductor device according to claim 1, wherein the insulating film is thicker than a gate insulating film.

7. The semiconductor device according to claim 6, wherein the insulating film covering a bottom surface of the trench is thicker than the insulating film covering a side surface of the trench.

8. The semiconductor device according to claim 1, wherein a relative permittivity of the insulating film is higher than a relative permittivity of the semiconductor substrate.