NANOSHEET TRANSISTORS WITH SHARP JUNCTIONS

• US 20180114834A1
• Filed: 10/24/2016
• Published: 04/26/2018
• Est. Priority Date: 10/24/2016
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Cheng, Kangguo, Clevenger, Lawrence A., Pranatharthi Haran, Balasubramanian S., Zhang, John
• Granted Patent: US 10,600,638 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/0214 the material being a silicon oxynitride, e.g. SiON or SiON:H
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/02167 the material being a silicon carbide not containing oxygen, e.g. SiC, SiC:H or silicon carbonitrides H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02236 group IV semiconductor
• CPC Class Codes: H01L 29/0665 the shape of the body defining a nanostructure nanotechnology per se B82B
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/778 with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface H01L29/803 takes precedence
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78654 Monocrystalline silicon transistors
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A method of forming a semiconductor device and resulting structures having nanosheet transistors with sharp junctions by forming a nanosheet stack over a substrate, the nanosheet stack having a plurality of nanosheets alternating with a plurality of sacrificial layers, such that a topmost and a bottommost layer of the nanosheet stack is a sacrificial layer; forming an oxide recess on a first and a second end of each sacrificial layer; and forming a doped extension region on a first and a second end of each nanosheet.

Claims

1. A method for forming a semiconductor device, the method comprising:

forming a nanosheet stack over a substrate, the nanosheet stack having a plurality of nanosheets alternating with a plurality of sacrificial layers, arranged such that a topmost and a bottommost layer of the nanosheet stack is one of the sacrificial layers;

forming an oxide recess on a first and a second end of each sacrificial layer; and

forming a doped extension region on a first and a second end of each nanosheet.

2. The method of claim 1, further comprising:

forming a dielectric layer on the nanosheet stack;

forming a sacrificial gate having a first and a second gate sidewall on the dielectric layer, a top surface of the sacrificial gate covered by a hard mask;

forming a first outer spacer on the first gate sidewall and a first surface of the hard mask;

forming a second outer spacer on the second gate sidewall and a second surface of the hard mask;

removing a portion of the nanosheet stack to expose first and second ends of the nanosheet stack and a portion of the substrate;

forming a first and a second epitaxy on the exposed portions of the substrate;

forming an interlayer dielectric (ILD) on the first and second epitaxy; and

replacing the sacrificial gate and sacrificial layers with a metal gate having a high-k dielectric liner.

3. The method of claim 1, wherein forming an oxide recess on a first and second end of each sacrificial layer further comprises:

exposing the nanosheet stack to an oxidant, the oxidant preferentially diffusing into the first and second end of each sacrificial layer, which causes displacing a first material in the first and second end of each sacrificial layer to the first and second end of each nanosheet;

wherein an extension region on the first and second end of each nanosheet is defined by the displaced first material in the first and second end of each nanosheet.

4. The method of claim 3, wherein forming a doped extension region on a first and second end of each nanosheet further comprises exposing the nanosheet stack to a dopant, the dopant doping the extension region on the first and second end of each nanosheet.

5. The method of claim 1, wherein each nanosheet is silicon, each sacrificial layer is silicon germanium (SiGe), the doped extension region is doped SiGe, and the oxide recess is a silicon oxide (SiO).

6. The method of claim 1, wherein each nanosheet has a thickness of about 2 nm to about 10 nm, and wherein each sacrificial layer has a thickness of about 2 nm to about 10 nm.

7. The method of claim 1, wherein each sacrificial layer comprises about 20 percent to about 75 percent silicon germanium (SiGe).

8. The method of claim 1, wherein the doped extension region extends into the first and second end of each nanosheet about 3 nm to about 12 nm.

9. The method of claim 1, wherein the doped extension region extends into the first and second end of each nanosheet about 5 nm to about 8 nm.

10. The method of claim 2, wherein the first outer spacer and the second outer spacer are a silicoboron carbonitride (SiBCN) or a silicon oxide carbonitride (SiOCN).

11. (canceled)

12. (canceled)

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16. (canceled)

17. (canceled)

18. A method for forming a semiconductor device, the method comprising:

forming a nanosheet stack over a substrate, the nanosheet stack having a plurality of silicon nanosheets alternating with a plurality of silicon germanium (SiGe) sacrificial layers, arranged such that a topmost and a bottommost layer of the nanosheet stack is one of the sacrificial layers;

oxidizing a first and a second end of each SiGe sacrificial layer to form a silicon oxide (SiO) recess, which causes displacement of germanium in the first and second end of each sacrificial layer to a first and a second end of each silicon nanosheet; and

exposing the nanosheet stack to a dopant, the dopant doping a SiGe extension region on the first and second end of each silicon nanosheet, the SiGe extension region defined by the displaced germanium in the first and second end of each silicon nanosheet.

19. The method of claim 18, wherein each nanosheet has a thickness of about 2 nm to about 10 nm, and wherein each sacrificial layer has a thickness of about 2 nm to about 10 nm.

20. The method of claim 18, wherein each sacrificial layer comprises about 20 percent to about 75 percent SiGe.