SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

• US 20180114844A1
• Filed: 12/14/2017
• Published: 04/26/2018
• Est. Priority Date: 11/07/2008
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: YAMAZAKI, Shunpei, AKIMOTO, Kengo, KAWAE, Daisuke
• Granted Patent: US 10,411,102 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/786 Thin film transistors, i.e. transistors with a channel being at least partly a thin film transistors having only the source or the drain region on an insulator layer H01L29/0653; thin film FinFETs H01L29/785
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10K 10/46 Field-effect transistors, e.g. organic thin-film transistors [OTFT] H10K10/43 takes precedence
• CPC Class Codes: H10K 10/462 Insulated gate field-effect transistors [IGFETs]
• CPC Class Codes: H10K 10/466 Lateral bottom-gate IGFETs comprising only a single gate
• CPC Class Codes: H10K 10/84 Ohmic electrodes, e.g. source or drain electrodes

Abstract

A structure by which electric-field concentration which might occur between a source electrode and a drain electrode in a bottom-gate thin film transistor is relaxed and deterioration of the switching characteristics is suppressed, and a manufacturing method thereof. A bottom-gate thin film transistor in which an oxide semiconductor layer is provided over a source and drain electrodes is manufactured, and angle θ1 of the side surface of the source electrode which is in contact with the oxide semiconductor layer and angle θ2 of the side surface of the drain electrode which is in contact with the oxide semiconductor layer are each set to be greater than or equal to 20° and less than 90°, so that the distance from the top edge to the bottom edge in the side surface of each electrode is increased.

Claims

1. (canceled)

2. A semiconductor device comprising:

a transistor over a first substrate, the transistor comprising;

a source electrode layer and a drain electrode layer; and

a first oxide semiconductor layer over the source electrode layer and the drain electrode layer,

wherein;

part of the first oxide semiconductor layer is positioned between a side surface of the source electrode layer and a side surface of the drain electrode layer facing each other;

an angle between a surface of the first substrate and the side surface of the source electrode layer is greater than or equal to 20° and

less than or equal to 90°

; and

an angle between the surface of the first substrate and the side surface of the drain electrode layer is greater than or equal to 20° and

less than or equal to 90°

.

3. The semiconductor device according to claim 2, wherein the first oxide semiconductor layer comprises indium, zinc, and oxygen.

4. The semiconductor device according to claim 3, wherein the first oxide semiconductor layer comprises gallium.

5. The semiconductor device according to claim 2,

wherein the transistor comprises a gate electrode layer and a gate insulating layer over the gate electrode layer, and

wherein the source electrode layer and the drain electrode layer are over and in contact with the gate insulating layer.

6. The semiconductor device according to claim 2, wherein each of the side surface of the source electrode layer and the side surface of the drain electrode layer has a step at a bottom edge thereof.

7. The semiconductor device according to claim 2, wherein the first oxide semiconductor layer is in contact with the side surface of the source electrode layer and the side surface of the drain electrode layer.

8. A display device comprising:

the semiconductor device according to claim 2; and

a pixel electrode electrically connected to any of the source electrode layer and the drain electrode layer.

9. A semiconductor device comprising:

a transistor over a first substrate, the transistor comprising;

a source electrode layer and a drain electrode layer;

a first buffer layer over the source electrode layer;

a second buffer layer over the drain electrode layer; and

a first oxide semiconductor layer over the first buffer layer and the second buffer layer,

wherein;

part of the first oxide semiconductor layer is positioned between a side surface of the source electrode layer and a side surface of the drain electrode layer facing each other;

an angle between a surface of the first substrate and the side surface of the source electrode layer is greater than or equal to 20° and

less than or equal to 90°

; and

an angle between the surface of the first substrate and the side surface of the drain electrode layer is greater than or equal to 20° and

less than or equal to 90°

.

10. The semiconductor device according to claim 9, wherein the first oxide semiconductor layer comprises indium, zinc, and oxygen.

11. The semiconductor device according to claim 10, wherein the first oxide semiconductor layer comprises gallium.

12. The semiconductor device according to claim 9,

wherein the transistor comprises a gate electrode layer and a gate insulating layer over the gate electrode layer, and

wherein the source electrode layer and the drain electrode layer are over and in contact with the gate insulating layer.

13. The semiconductor device according to claim 9, wherein each of the side surface of the source electrode layer and the side surface of the drain electrode layer has a step at a bottom edge thereof.

14. The semiconductor device according to claim 9, wherein the first oxide semiconductor layer is in contact with the side surface of the source electrode layer and the side surface of the drain electrode layer.

15. The semiconductor device according to claim 9, wherein a resistance of each of the first buffer layer and the second buffer layer is lower than a resistance of the first oxide semiconductor layer.

16. A display device comprising:

the semiconductor device according to claims 9; and

a pixel electrode electrically connected to any of the source electrode layer and the drain electrode layer.

17. A semiconductor device comprising:

a transistor over a first substrate, the transistor comprising;

a source electrode layer and a drain electrode layer;

a first oxide semiconductor layer over the source electrode layer;

a second oxide semiconductor layer over the drain electrode layer; and

a third oxide semiconductor layer over the first oxide semiconductor layer and the second oxide semiconductor layer,

wherein;

part of the third oxide semiconductor layer is positioned between a side surface of the source electrode layer and a side surface of the drain electrode layer facing each other;

an angle between a surface of the first substrate and the side surface of the source electrode layer is greater than or equal to 20° and

less than or equal to 90°

; and

an angle between the surface of the first substrate and the side surface of the drain electrode layer is greater than or equal to 20° and

less than or equal to 90°

.

18. The semiconductor device according to claim 17, wherein the third oxide semiconductor layer comprises indium, zinc, and oxygen.

19. The semiconductor device according to claim 18, wherein the third oxide semiconductor layer comprises gallium.

20. The semiconductor device according to claim 17, wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer comprises indium, zinc, and oxygen.

21. The semiconductor device according to claim 20, wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer comprises gallium.

22. The semiconductor device according to claim 17,

wherein the transistor comprises a gate electrode layer and a gate insulating layer over the gate electrode layer, and

wherein the source electrode layer and the drain electrode layer are over and in contact with the gate insulating layer.

23. The semiconductor device according to claim 17, wherein each of the side surface of the source electrode layer and the side surface of the drain electrode layer has a step at a bottom edge thereof.

24. The semiconductor device according to claim 17, wherein the third oxide semiconductor layer is in contact with the side surface of the source electrode layer and the side surface of the drain electrode layer.

25. The semiconductor device according to claim 17, wherein a resistance of each of the first oxide semiconductor layer and the second oxide semiconductor layer is lower than a resistance of the third oxide semiconductor layer.

26. A display device comprising:

the semiconductor device according to claim 17; and

a pixel electrode electrically connected to any of the source electrode layer and the drain electrode layer.