Configurable Clamp Circuit

• US 20180115311A1
• Filed: 10/24/2016
• Published: 04/26/2018
• Est. Priority Date: 10/24/2016
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Norling, Karl, Huber, Erwin
• Granted Patent: US 10,461,737 B2
• Time in Patent Office: Days
• CPC Class Codes: G05F 3/02 Regulating voltage or current
• CPC Class Codes: H03K 17/06 Modifications for ensuring a fully conducting state
• CPC Class Codes: H03K 17/168 in composite switches
• CPC Class Codes: H03K 17/6872 using complementary field-effect transistors
• CPC Class Codes: H03K 2017/066 Maximizing the OFF-resistance instead of minimizing the ON-resistance
• CPC Class Codes: H03K 5/08 by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding H03K5/07 takes precedence; comparing one pulse with another H03K5/22; providing a determined threshold for switching H03K17/30

Abstract

In accordance with an embodiment of the present invention, a circuit includes a configurable clamp driver circuit for clamping a voltage at a gate terminal of a transistor below a turn-on voltage threshold upon switch-off of the transistor. In a first clamp driver circuit mode, an output terminal of the clamp driver circuit is configured to be coupled to the gate terminal of the transistor to provide a first discharge path from the gate terminal of the transistor upon switch-off of the transistor. In a second clamp driver circuit mode, the output terminal of the clamp driver circuit is configured to be coupled to an input terminal of a clamp circuit, wherein the clamp circuit is coupled to the gate terminal of the transistor to provide a second discharge path from the gate terminal of the transistor upon switch-off of the transistor.

Claims

1. A circuit comprising:

a configurable clamp driver circuit for clamping a voltage at a gate terminal of a first transistor below a turn-on voltage threshold upon switch-off of the first transistor, wherein the clamp driver circuit is configured to be operated in one of two modes, wherein;

in a first mode of the two modes, an output terminal of the clamp driver circuit is configured to be coupled to the gate terminal of the first transistor to provide a first discharge path for a current flowing from the gate terminal of the first transistor upon switch-off of the first transistor, the first discharge path bypassing a resistance coupled to the gate terminal of the first transistor; and

in a second mode of the two modes, the output terminal of the clamp driver circuit is configured to be coupled to an input terminal of a clamp circuit, wherein the clamp circuit is coupled to the gate terminal of the first transistor to provide a second discharge path for the current flowing from the gate terminal of the first transistor upon switch-off of the first transistor, the second discharge path bypassing the resistance coupled to the gate terminal of the first transistor.

2. The circuit of claim 1, further comprising the clamp circuit, the clamp circuit comprising a second transistor, wherein the gate terminal of the second transistor is coupled to the output terminal of the clamp driver circuit and an output terminal of the second transistor is coupled to the gate terminal of the first transistor.

3. The circuit of claim 1, wherein the clamp driver circuit is disposed on a semiconductor substrate and the clamp circuit is external to the semiconductor substrate.

4. The circuit of claim 1, wherein the first transistor is external to the clamp driver circuit.

5. The circuit of claim 1, wherein the first transistor is an IGBT.

6. The circuit of claim 1, wherein a polarity of a signal at the output terminal of the clamp driver circuit depends on the mode of the clamp driver circuit.

7. The circuit of claim 6, wherein the signal has a first polarity in the first mode and has a second polarity in the second mode that is opposite to the first polarity.

8. The circuit of claim 1, wherein an output stage of the clamp driver circuit comprises:

a pull-up circuit coupled between a first power supply terminal and the output terminal of the clamp driver circuit; and

a pull-down circuit coupled between a second power supply terminal and the output terminal of the clamp driver circuit.

9. The circuit of claim 8, wherein the pull-up circuit comprises a p-channel MOSFET and the pull-down circuit comprises an n-channel MOSFET.

10. The circuit of claim 8, further comprising a voltage regulator circuit coupled between a power supply terminal and the output stage of the clamp driver circuit.

11. The circuit of claim 8, further comprising a voltage limiter circuit coupled between a power supply terminal and the output stage of the clamp driver circuit.

12. The circuit of claim 11, wherein the voltage limiter circuit comprises a Zener diode.

13. The circuit of claim 1, further comprising a controller coupled to the clamp driver circuit, wherein the controller is configured to send a first control signal to the clamp driver circuit that indicates the clamp driver circuit mode and a second control signal to the clamp driver circuit that activates the clamp driver circuit.

14. An integrated circuit comprising:

a clamp driver circuit comprising a pull-up circuit and a pull-down circuit, the pull-up circuit and the pull-down circuit coupled to a gate-driver output terminal, wherein the gate-driver output terminal is configured to be coupled to an input terminal of a power transistor; and

a logic circuit coupled to the pull-up circuit and the pull-down circuit, wherein the logic circuit is configured to control the pull-up circuit and the pull-down circuit;

wherein the clamp driver circuit is configured to be coupled in either a first configuration or a second configuration, wherein;

in the first configuration, an output terminal of the clamp driver circuit is configured to be coupled to the gate terminal of the power transistor; and

in the second configuration, the output terminal of the clamp driver circuit is configured to be coupled to a gate terminal of an external clamp transistor, wherein an output terminal of the external clamp transistor is coupled to the gate terminal of the power transistor.

15. The integrated circuit of claim 14, further comprising the power transistor.

16. The integrated circuit of claim 14, wherein the power transistor is external to the clamp driver circuit.

17. The integrated circuit of claim 14, wherein the clamp driver circuit is configured to dissipate current from the gate terminal of the power transistor.

18. The integrated circuit of claim 14, wherein the power transistor comprises an IGBT.

19. The integrated circuit of claim 14, further comprising a voltage limiting circuit coupled to the clamp driver circuit and configured to limit the voltage at the output terminal of the clamp driver circuit.

20. The integrated circuit of claim 19, wherein the voltage limiting circuit comprises a Zener diode.

21. The integrated circuit of claim 14 wherein the clamp driver circuit comprises a pull-up circuit coupled to the output terminal of the clamp driver circuit and a pull-down circuit coupled to the output terminal of the clamp driver circuit.

22. The integrated circuit of claim 21, wherein the pull-up circuit comprises a p-channel MOSFET and the pull-down circuit comprises an n-channel MOSFET.

23. A method comprising:

configuring a clamp driver circuit in one of two configurations, wherein;

configuring the clamp driver circuit in a first configuration comprises coupling an output terminal of the clamp driver circuit to a gate terminal of a first transistor; and

configuring the clamp driver circuit in a second configuration comprises coupling the output terminal of the clamp driver circuit to a gate terminal of a clamp transistor, wherein an output terminal of the clamp transistor is coupled to the gate terminal of the first transistor;

switching off the first transistor; and

activating the clamp driver circuit.

24. The method of claim 23, wherein configuring the clamp driver circuit further comprises receiving a control signal at the clamp driver circuit, the control signal indicating the configuration of the clamp driver circuit.

25. The method of claim 23, further comprising limiting the voltage at the output terminal of the clamp driver circuit.

26. The method of claim 23, wherein activating the clamp driver circuit comprises providing a low-resistance path from the gate terminal of the first transistor to a voltage supply.