Thread Importance Based Processor Core Parking And Frequency Selection

• US 20180120920A1
• Filed: 05/30/2017
• Published: 05/03/2018
• Est. Priority Date: 11/01/2016
• Status: Active Grant

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Inventors: IYIGUN, Mehmet, HSU, Kai-Lun, NAIR, Rahul, BELLON, Mark Allan, KISHAN, Arun U., BROWN, Tristan A.
• Granted Patent: US 10,503,238 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3243 Power saving in microcontroller unit
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 1/329 by task scheduling
• CPC Class Codes: G06F 9/226 Microinstruction function, e.g. input/output microinstruction; diagnostic microinstruction; microinstruction format
• CPC Class Codes: G06F 9/3009 Thread control instructions
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/46 Multiprogramming arrangements
• CPC Class Codes: G06F 9/5005 to service a request
• CPC Class Codes: G06F 9/5044 considering hardware capabilities
• CPC Class Codes: G06F 9/505 considering the load
• CPC Class Codes: G06F 9/5094 where the allocation takes into account power or heat criteria power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Each processor core in a computing device supports various different frequency ranges, also referred to as p-states, and can operate to run threads at any one of those different frequency ranges. Threads in the computing device are assigned one of multiple importance levels. A processor core is configured to run at a particular frequency range or in accordance with a particular energy performance preference based on the importance level of the thread it is running. A utilization factor of a processor core can also be determined over some time duration, the utilization factor being based on the amount of time during the time duration that the processor core was running a thread(s), and also based on the importance levels of the thread(s) run during the time duration. The utilization factor can then be used to determine whether to park the processor core.

Claims

1. A method comprising:

determining an importance level of a first thread scheduled to run on a processor core, the importance level being one of multiple different importance levels;

determining a frequency range associated with the importance level that is one of multiple different frequency ranges or an energy performance preference value associated with the importance level that is one of multiple energy performance preference values; and

configuring the processor core to run at the frequency range or in accordance with the energy performance preference value while running the first thread.

2. The method as recited in claim 1, the determining a frequency range or an energy performance preference value comprising determining the frequency range, each frequency range having been determined based on efficiency of the processor core at each of multiple different frequencies at which the processor core can run.

3. The method as recited in claim 1, the multiple different importance levels including an important level and an unimportant level, the importance level of the first thread comprising the unimportant level, and the frequency range associated with the unimportant level comprising a frequency range including one or more frequencies within a threshold amount of a most efficient frequency of the processor core.

4. The method as recited in claim 1, further comprising:

programmatically determining the efficiency of the processor core at each of multiple different frequencies at which the processor core can run; and

identifying, based on the determined efficiencies, the frequency range associated with each of the multiple different importance levels.

5. The method as recited in claim 1, the multiple different importance levels comprising two or more quality of service levels.

6. The method as recited in claim 1, the configuring the processor core comprising writing an indication of the frequency range to one or more registers of the processor core.

7. The method as recited in claim 1, the configuring the processor core comprising including an indication of the importance level in context information provided to the processor core when the processor core switches contexts to being running the first thread.

8. The method as recited in claim 1, the determining a frequency range or an energy performance preference value comprising determining the energy performance preference value, the energy performance preference value indicating to the processor core whether to prefer high performance or lower energy usage while running the first thread.

9. The method as recited in claim 1, further comprising:

determining a utilization factor of the processor core based at least in part on the importance levels of threads run on the processor core over a given time duration; and

determining, based on the utilization factor of the processor core, whether to park the processor core.

10. A method comprising:

determining, for each of multiple threads run on a processor core over a given time duration, an importance level of the thread, each importance level being one of multiple different importance levels;

determining a utilization factor of the processor core based at least in part on the importance levels of the threads run on the processor core over the given time duration;

determining, based on the utilization factor of the processor core, whether to park the processor core; and

parking the processor core in response to determining to park the processor core based on the utilization factor of the processor core.

11. The method as recited in claim 10, the determining the utilization factor comprising excluding from consideration in determining the utilization factor one or more of the multiple threads having less than a threshold importance level.

12. The method as recited in claim 10, the determining the utilization factor comprising weighting, for each of the threads run on the processor core over the given time duration, the thread based on the importance level of the thread.

13. The method as recited in claim 10, further comprising:

determining, based on utilization factors or one or more additional processor cores, to unpark the parked processor core; and

unparking the parked processor core.

14. A computing device comprising:

one or more processor cores;

a thread importance determination module configured to determine an importance level of a first thread scheduled to run on a processor core of the one or more processor cores, the importance level being one of multiple different importance levels; and

a core frequency configuration module configured to determine a frequency range associated with the importance level that is one of multiple different frequency ranges or an energy performance preference value associated with the importance level that is one of multiple energy performance preference values, and to configure the processor core to run at the frequency range or in accordance with the energy performance preference value while running the first thread.

15. The computing device as recited in claim 14, the core frequency configuration module being further configured to determine the frequency range, each frequency range having been determined based on efficiency of the processor core at each of multiple different frequencies at which the processor core can run.

16. The computing device as recited in claim 14, the multiple different importance levels including an important level and an unimportant level, the importance level of the first thread comprising the unimportant level, and the frequency range associated with the unimportant level comprising a frequency range including one or more frequencies within a threshold amount of a most efficient frequency of the processor core.

17. The computing device as recited in claim 14, the core frequency configuration module being further configured to determine the energy performance preference value, the energy performance preference value indicating to the processor core whether to prefer high performance or lower energy usage while running the first thread.

18. The computing device as recited in claim 14, further comprising a core parking module configured to determine a utilization factor of the processor core based at least in part on the importance levels of multiple threads run on the processor core over a given time duration, and to determine, based on the utilization factor of the processor core, whether to park the processor core.

19. The computing device as recited in claim 18, the core parking module being further configured to determine the utilization factor by excluding from consideration in determining the utilization factor one or more of the multiple threads having less than a threshold importance level.

20. The computing device as recited in claim 18, the determining the utilization factor comprising weighting, for each of the threads run on the processor core over the given time duration, the thread based on the importance level of the thread.