GATE DRIVER AND DISPLAY DEVICE HAVING IN-CELL TOUCH SENSOR USING THE SAME

• US 20180121023A1
• Filed: 10/30/2017
• Published: 05/03/2018
• Est. Priority Date: 10/31/2016
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: KIM, Yeonkyung, MOON, Taewoong, LEE, Junghyun
• Granted Patent: US 10,534,477 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 3/0412 Digitisers structurally integrated in a display
• CPC Class Codes: G06F 3/04184 Synchronisation with the driving of the display or the backlighting unit to avoid interferences generated internally
• CPC Class Codes: G06F 3/0443 using a single layer of sensing electrodes
• CPC Class Codes: G09G 2300/0809 Several active elements per pixel in active matrix panels
• CPC Class Codes: G09G 2300/0866 by means of changes in the pixel supply voltage
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/0291 Details of output amplifiers or buffers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2354/00 Aspects of interface with display user
• CPC Class Codes: G09G 3/3677 suitable for active matrices only

Abstract

A gate driver and a display device having an in-cell touch sensor using the gate driver are disclosed. The gate driver includes a shift register configured to sequentially supply gate pulses to gate lines of a display panel. The shift register includes an (N−1)th stage, where N is a positive integer equal to or greater than 2, configured to output an (N−1)th gate pulse, an Nth stage configured to output an Nth gate pulse, and a hold circuit configured to hold an output voltage of the (N−1)th stage during a predetermined time and supply the output voltage to the Nth stage.

Claims

1. A gate driver comprising:

a shift register configured to sequentially supply gate pulses to gate lines of a display panel, the shift register including;

an (N−

1)th stage, where N is a positive integer equal to or greater than 2, configured to output an (N−

1)th gate pulse;

an Nth stage configured to output an Nth gate pulse; and

a hold circuit configured to hold an output voltage of the (N−

1)th stage during a predetermined time and supply the output voltage to the Nth stage.

2. The gate driver of claim 1, wherein the predetermined time includes a touch sensing period of the display panel.

3. The gate driver of claim 1, wherein the output voltage of the (N−

1)th stage includes at least one of the (N−

1)th gate pulse, a carry signal transmitted to another stage, and a separate output voltage different from the (N−

1)th gate pulse and the carry signal.

4. The gate driver of claim 1, wherein the hold circuit is connected between an output terminal of the (N−

1)th stage and a start input terminal of the Nth stage, stores the output voltage of the (N−

1)th stage during the predetermined time, and supplies the stored voltage to the start input terminal of the Nth stage before an end of the predetermined time,

wherein the (N−

1)th stage generates the output voltage through the output terminal when a first clock signal is input,

wherein each of the (N−

1)th stage and the Nth stage includes a respective pull-up transistor having a gate connected to a respective Q node and configured to raise a voltage of a respective gate pulse depending on a voltage of the Q node, and

wherein the Q node of the Nth stage is charged based on the output voltage supplied through the hold circuit.

5. The gate driver of claim 4, wherein the hold circuit includes:

a first transistor including a gate connected to the output terminal of the (N−

1)th stage, a first electrode to which a second clock signal that is generated following the first clock is applied, and a second electrode connected to a hold node;

a second transistor including a gate to which a third clock signal that is generated following the second clock signal is applied, a first electrode connected to the hold node, and a second electrode connected to the start input terminal of the Nth stage;

a third transistor including a gate to which at least one of an output voltage of the Nth stage or a fourth clock signal that is generated following the output voltage of the Nth stage is applied, a first electrode connected to the hold node, and a second electrode to which a gate-off voltage is applied; and

a capacitor including a first electrode connected to the hold node and a second electrode to which the gate-off voltage is applied,

wherein the gate-off voltage is lower than a threshold voltage of each of the first, second, and third transistors.

6. The gate driver of claim 5, wherein the Q node of the Nth stage maintains an uncharged state during the predetermined time except for a portion of the predetermined time in which the third clock signal is generated, and is charged when the second transistor is turned on based on the third clock signal.

7. The gate driver of claim 5, wherein the first, second, and third transistors include an oxide semiconductor.

8. A display device comprising:

a display panel in which data lines and gate lines are arranged in intersecting directions, pixels are arranged in a matrix form, a screen including the pixels and touch sensors is divided into at least first and second blocks, and the first and second blocks are time-divisionally driven during first and second display periods, respectively, with a touch sensing period between the first and second display periods;

a display driver configured to drive pixels of the first block during the first display period, drive pixels of the second block during the second display period after the touch sensing period, and write data of an input image to the pixels of the first and second blocks; and

a touch sensing unit configured to sense a touch input by driving the touch sensors during the touch sensing period,

wherein the display driver includes a shift register configured to sequentially supply gate pulses to the gate lines, the shift register including;

an (N−

1)th stage, where N is a positive integer equal to or greater than 2, configured to output a last gate pulse of the first display period;

an Nth stage configured to output a first gate pulse of the second display period at a time corresponding to a start of the second display period after the touch sensing period; and

a hold circuit configured to hold an output voltage of the (N−

1)th stage during the touch sensing period and supply the output voltage to the Nth stage.

9. The display device of claim 8, wherein the output voltage of the (N−

1)th stage includes at least one of the last gate pulse of the first display period, a carry signal transmitted to another stage, and a separate output voltage different from the last gate pulse of the first display period and the carry signal.

10. The display device of claim 8, wherein the hold circuit is connected between an output terminal of the (N−

1)th stage and a start input terminal of the Nth stage, stores the output voltage of the (N−

1)th stage during the touch sensing period, and supplies the stored voltage to the start input terminal of the Nth stage before an end of the touch sensing period,

wherein the (N−

1)th stage generates the output voltage through the output terminal based on a first clock signal,

wherein each of the (N−

1)th stage and the Nth stage includes a respective pull-up transistor having a gate connected to a respective Q node and configured to raise a voltage of a respective gate pulse depending on a voltage of the Q node, and

wherein the Nth stage charges the Q node based on the output voltage supplied through the hold circuit.

11. The display device of claim 10, wherein the hold circuit includes:

a first transistor including a gate connected to the output terminal of the (N−

1)th stage, a first electrode to which a second clock signal that is generated following the first clock signal is applied, and a second electrode connected to a hold node;

a second transistor including a gate to which a third clock signal that is generated following the second clock is applied, a first electrode connected to the hold node, and a second electrode connected to the start input terminal of the Nth stage;

a third transistor including a gate to which at least one of an output voltage of the Nth stage or a fourth clock signal that is generated following the output voltage of the Nth stage is applied, a first electrode connected to the hold node, and a second electrode to which a gate-off voltage is applied; and

a capacitor including a first electrode connected to the hold node and a second electrode to which the gate-off voltage is applied,

wherein the gate-off voltage is lower than a threshold voltage of each of the first, second, and third transistors.

12. The display device of claim 11, wherein the Q node of the Nth stage maintains an uncharged state during the touch sensing period except for a portion of the touch sensing period in which the third clock signal is generated, and is charged when the second transistor is turned on based on the third clock signal.

13. A display device, comprising:

a pixel array;

a plurality of gate lines, each of the gate lines coupled to a respective plurality of pixels of the pixel array;

a plurality of touch sensors embedded in the pixel array; and

a gate driver including a shift register configured to sequentially supply gate pulses to the gate lines, the shift register including;

a first stage coupled to a first gate line of the plurality of gate lines;

a second stage coupled to a second gate line of the plurality of gate lines; and

a hold circuit coupled between the first stage and the second stage, the hold circuit configured to hold a voltage in response to receiving an output of the first stage.

14. The display device of claim 13, wherein the hold circuit includes:

a capacitor having a first electrode and a second electrode; and

a first transistor having a gate terminal coupled to the output of the first stage, a first conduction terminal coupled to a first clock output, and a second conduction terminal coupled to the first electrode of the capacitor, wherein the first transistor supplies a voltage of the first clock output to the first electrode of the capacitor in response to receiving the output of the first stage at the gate terminal of the first transistor.

15. The display device of claim 14, wherein the hold circuit further includes a second transistor having a gate terminal coupled to a second clock output, a first conduction terminal coupled to the first electrode of the capacitor, and a second conduction terminal coupled to an input of the second stage, wherein the second transistor supplies the voltage of the first clock output to the input of the second stage based on the second clock output.

16. The display device of claim 15, wherein the hold circuit further includes a third transistor having a gate terminal, a first conduction terminal coupled to the first electrode of the capacitor, and a second conduction terminal coupled to the second electrode of the capacitor.

17. The display device of claim 16 wherein the gate terminal of the third transistor is coupled to a third clock output, and the third transistor is configured to discharge the capacitor based on the third clock output.

18. The display device of claim 16 wherein the gate terminal of the third transistor is coupled to an output of the second stage, and the third transistor is configured to discharge the capacitor based on the output of the second stage.

19. The display device of claim 13, further comprising:

a plurality of touch sensor lines, each of the touch sensor lines coupled to a respective touch sensor; and

a touch sensing unit coupled to the touch sensor lines and configured to drive the touch sensors during a touch sensing period, wherein the touch sensing period is interposed between a first display period in which the first stage outputs a first gate pulse to the first gate line and a second display period in which the second stage outputs a second gate pulse to the second gate line.

20. The display device of claim 19, wherein the hold circuit is configured to hold the voltage for an entire duration of the touch sensing period.