METHOD OF FLUSHING THE CONTENTS OF A DYNAMIC REDUNDANCY REGISTER TO A SECURE STORAGE AREA DURING A POWER DOWN IN A MEMORY DEVICE

• US 20180121355A1
• Filed: 12/27/2017
• Published: 05/03/2018
• Est. Priority Date: 09/27/2016
• Status: Active Grant

• Current Assignee: Integrated Silicon Solution Incorporated (Uphill Investment Co.)
• Original Assignee: Spin Transfer Technologies, Inc.
• Inventors: BERGER, Neal, LOUIE, Benjamin, EL-BARAJI, Mourad, CRUDELE, Lester, HILLMAN, Daniel
• Granted Patent: US 10,437,723 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/205 Hybrid memory, e.g. using both volatile and non-volatile memory
• CPC Class Codes: G11C 11/1653 Address circuits or decoders
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 11/1677 Verifying circuits or methods
• CPC Class Codes: G11C 11/1697 Power supply circuits
• CPC Class Codes: G11C 2207/2227 Standby or low power modes
• CPC Class Codes: G11C 2207/2245 Memory devices with an internal cache buffer
• CPC Class Codes: G11C 2207/229 Timing of a write operation sense amplifier timing G11C7/06, G11C7/08
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method of writing data into a memory device is disclosed. The method comprises utilizing a pipeline to process write operations of a first plurality of data words addressed to a memory bank. Further, the method comprises writing a second plurality of data words and associated memory addresses into a cache memory, wherein the cache memory is associated with the memory bank and wherein further each data word of the second plurality of data words is either awaiting write verification associated with the memory bank or is to be re-written into the memory bank. The method also comprises detecting a power down signal and responsive to the power down signal, and before the memory device is powered down, processing data words of the second plurality of data words and associated memory addresses through the pipeline to write data into the memory bank. Finally, the method comprises powering down the memory device.

Claims

1. A method of writing data into a memory device, the method comprising:

utilizing a pipeline to process write operations of a first plurality of data words addressed to a memory bank;

writing a second plurality of data words and associated memory addresses into a cache memory, wherein said cache memory is associated with said memory bank and wherein further each data word of said second plurality of data words is either awaiting write verification associated with said memory bank or is to be re-written into said memory bank;

detecting a power down signal;

responsive to the power down signal, and before said memory device is powered down, processing data words of said second plurality of data words and associated memory addresses through said pipeline to write data into said memory bank; and

powering down the memory device.

2. A method as described in claim 1 wherein said memory bank comprises a plurality of spin-transfer torque magnetic random access memory (STT-MRAM) cells.

3. A method as described in claim 1 wherein said power down signal originates from a system level software stack and represents a system wide orderly power down event.

4. A method as described in claim 1 further comprising removing a data word and its associated address from said cache memory responsive to an indication that said data word has been verified as properly written to said memory bank.

5. A method as described in claim 1 further comprising:

subsequent to said processing said data words and before said power down, transferring any unprocessed data words of said second plurality of data words from said cache memory to a secure memory storage area of said memory bank.

6. A method as described in claim 5 wherein said transferring comprises utilizing a secure communication process substantially compliant with one of:

voting;

ECC encoding;

use of multiple copies;

comparing multiple copies; and

voting from multiple copies.

7. A method as described in claim 5, further comprising:

receiving a power up signal;

responsive to the power up signal, transferring any data words and associated memory addresses from the secure memory storage area to the cache memory; and

processing said data words, from said cache memory, through said pipeline for writing into said memory bank.

8. A memory device for storing data, the memory device comprising:

a memory bank comprising a plurality of addressable memory cells;

a pipeline configured to process write operations of a first plurality of data words addressed to said memory bank;

a cache memory operable for storing a second plurality of data words and associated memory addresses, wherein said cache memory is associated with said memory bank and wherein further each data word of said second plurality of data words is either awaiting write verification associated with said memory bank or is to be re-written into said memory bank; and

a logic module operable to;

detect a power down signal;

responsive to the power down signal, and before said memory device is powered down, process data words of said second plurality of data words and associated memory addresses through said pipeline to write data to said memory bank; and

power down the memory device.

9. A memory device as described in claim 8 wherein said plurality of addressable memory cells of said memory bank comprises spin-transfer torque magnetic random access memory (STT-MRAM) cells.

10. A memory device as described in claim 9 wherein said power down signal originates from a system level software stack and represents a system wide orderly power down event.

11. A memory device as described in claim 9 wherein a data word and its associated address are removed from said cache memory responsive to an indication that said data word has been verified as properly written to said memory bank.

12. A memory device as described in claim 8 wherein said logic module is further operable to, subsequent to said process said data words and before said power down, transfer any unprocessed data words of said second plurality of data words from said cache memory to a secure memory storage area of said memory bank.

13. A memory device as described in claim 12 wherein said logic module utilizes a secure communication process substantially compliant with one of:

voting;

ECC encoding;

use of multiple copies;

comparing multiple copies; and

voting from multiple copies.

14. A memory device as described in claim 12 wherein said logic module is further operable to:

detect a power up signal;

responsive to the power up signal, transfer any data words and associated memory addresses from the secure memory storage area to the cache memory; and

cause said pipeline to process said data words, from said cache memory, for writing into said memory bank.

15. A method of writing data into a memory device, the method comprising:

utilizing a pipeline to process write operations of a first plurality of data words addressed to a memory bank;

writing a second plurality of data words and associated memory addresses into a cache memory, wherein said cache memory is associated with said memory bank and wherein further each data word of said second plurality of data words is either awaiting write verification associated with said memory bank or is to be re-written into said memory bank;

detecting a power down signal;

responsive to the power down signal, and before said memory device is powered down, processing a first set of data words of said second plurality of data words and associated memory addresses through said pipeline to write data into said memory bank;

after said processing said first set of data words, and before said memory device is powered down, transferring a second set of data words of said second plurality of data words and associated memory addresses to a secure memory storage area of said memory bank; and

powering down the memory device.

16. A method as described in claim 15 wherein said memory bank comprises a plurality of spin-transfer torque magnetic random access memory (STT-MRAM) cells.

17. A method as described in claim 15 wherein said power down signal originates from a system level software stack and represents a system wide orderly power down event.

18. A method as described in claim 15 further comprising removing a data word and its associated memory address from said cache memory responsive to an indication that said data word has been verified as properly written to said memory bank.

20. A method as described in claim 18 wherein said transferring comprises utilizing a secure communication process substantially compliant with one of:

voting;

ECC encoding;

use of multiple copies;

comparing multiple copies; and

voting from multiple copies.

19. A method as described in claim 19, further comprising:

receiving a power up signal;

responsive to the power up signal, transferring said second set of data words and associated memory addresses from the secure memory storage area to the cache memory; and

processing said second set of data words, from said cache memory, through said pipeline for writing into said memory bank.