MEMORY DEVICE WITH A PLURALITY OF MEMORY BANKS WHERE EACH MEMORY BANK IS ASSOCIATED WITH A CORRESPONDING MEMORY INSTRUCTION PIPELINE AND A DYNAMIC REDUNDANCY REGISTER

• US 20180121361A1
• Filed: 12/27/2017
• Published: 05/03/2018
• Est. Priority Date: 09/27/2016
• Status: Active Grant

• Current Assignee: Integrated Silicon Solution Incorporated (Uphill Investment Co.)
• Original Assignee: Spin Transfer Technologies, Inc.
• Inventors: BERGER, Neal, Louie, Benjamin, EL-baraji, Mourad, Crudele, Lester, Hillman, Daniel
• Granted Patent: US 10,628,316 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 12/0215 with look ahead addressing means
• CPC Class Codes: G06F 12/0855 Overlapped cache accessing, e.g. pipeline G06F12/0846 takes precedence
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 12/0891 using clearing, invalidating or resetting means
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/202 Non-volatile memory
• CPC Class Codes: G11C 11/1653 Address circuits or decoders
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 11/1677 Verifying circuits or methods
• CPC Class Codes: G11C 11/1693 Timing circuits or methods
• CPC Class Codes: G11C 11/1697 Power supply circuits
• CPC Class Codes: G11C 2029/4402 Internal storage of test result, quality data, chip identification, repair information
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 29/74 using duplex memories, i.e. using dual copies
• CPC Class Codes: G11C 29/76 using address translation or modifications
• CPC Class Codes: G11C 5/143 Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels G11C5/148 takes precedence; Switching between alternative supplies G11C5/141 takes precedence
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers

Abstract

A memory device for storing data is disclosed. The memory device comprises a plurality of memory banks, wherein each memory bank comprises a plurality of addressable memory cells. The memory device also comprises a plurality of pipelines each comprising a plurality of pipestages, wherein each pipeline is associated with a respective one of the plurality of memory banks. Further, the device comprises a plurality of cache memories, wherein each cache memory is associated with a respective one of the plurality of memory banks and a respective one of the plurality of pipelines, and wherein each cache memory is operable for storing a second plurality of data words and associated memory addresses, and wherein further each data word of said second plurality of data words is either awaiting write verification associated with a given segment of an associated memory bank or is to be re-written into a given segment of said associated memory bank.

Claims

1. A memory device for storing data, the memory device comprising:

a plurality of memory banks, wherein each memory bank comprises a plurality of addressable memory cells;

a plurality of pipelines each comprising a plurality of pipestages, wherein each pipeline is associated with a respective one of the plurality of memory banks, and wherein each pipeline is configured to process write operations of a first plurality of data words addressed to its associated memory bank; and

a plurality of cache memories, wherein each cache memory is associated with a respective one of the plurality of memory banks and a respective one of the plurality of pipelines, and wherein each cache memory is operable for storing a second plurality of data words and associated memory addresses, and wherein further each data word of said second plurality of data words is either awaiting write verification associated with a given segment of an associated memory bank or is to be re-written into a given segment of said associated memory bank.

2. A memory device as described in claim 1, wherein said addressable memory cells of said associated memory bank comprise spin-transfer torque magnetic random access memory (STT-MRAM) cells.

3. A memory device as described in claim 1, wherein each pipeline is operable to flush a currently processing first memory operation to an associated cache memory if a second memory operation that enters the pipeline has a different row address as the first memory operation.

4. A memory device as described in claim 1, wherein each cache memory comprises one or more status indicators for indicating a partial occupancy level of said cache memory.

5. A memory device as described in claim 1, wherein each pipeline supports multiple write attempts for a given write operation.

6. A memory device as described in claim 1, wherein each pipeline supports a pre-read operation for a given write operation.

7. A memory device for storing data, the memory device comprising:

a plurality of memory banks, wherein each memory bank comprises a plurality of addressable memory cells;

a plurality of pipelines each comprising a plurality of pipestages, wherein each pipeline is associated with a respective one of the plurality of memory banks, and wherein each pipeline is configured to process write operations of a first plurality of data words addressed to its associated memory bank; and

a cache memory associated with each of the plurality of memory banks and each of the plurality of pipelines, and wherein the cache memory is operable for storing a second plurality of data words and associated memory addresses, and wherein further each data word of said second plurality of data words is either awaiting write verification associated with a given segment of an associated memory bank or is to be re-written into a given segment of the associated memory bank.

8. A memory device as described in claim 7, wherein said addressable memory cells of said associated memory bank comprise spin-transfer torque magnetic random access memory (STT-MRAM) cells.

9. A memory device as described in claim 7, wherein each pipeline is operable to flush a currently processing first memory operation to the cache memory if a second memory operation that enters the pipeline has a different row address as the first memory operation.

10. A memory device as described in claim 7, wherein the cache memory comprises one or more status indicators for indicating a partial occupancy level of the cache memory.

11. A memory device as described in claim 7, wherein each pipeline supports multiple write attempts for a given write operation.

12. A memory device as described in claim 7, wherein each pipeline supports a pre-read operation for a given write operation.

13. A memory device for storing data, the memory device comprising:

a plurality of memory banks, wherein each memory bank comprises a plurality of addressable memory cells, wherein the addressable memory cells of an associated memory bank comprise spin-transfer torque magnetic random access memory (STT-MRAM) cells;

a plurality of pipelines each comprising a plurality of pipestages, wherein each pipeline is associated with a respective one of the plurality of memory banks, and wherein each pipeline is configured to process write operations of a first plurality of data words addressed to its associated memory bank; and

a plurality of cache memories, wherein each cache memory is associated with a respective one of the plurality of memory banks and a respective one of the plurality of pipelines, and wherein each cache memory is operable for storing a second plurality of data words and associated memory addresses, and wherein further each data word of said second plurality of data words is either awaiting write verification associated with a given segment of an associated memory bank or is to be re-written into a given segment of said associated memory bank.

14. A memory device as described in claim 13, wherein each pipeline is operable to flush a currently processing first memory operation to an associated cache memory if a second memory operation that enters the pipeline has a different row address as the first memory operation.

15. A memory device as described in claim 13, wherein each cache memory comprises one or more status indicators for indicating a partial occupancy level of said cache memory.

16. A memory device as described in claim 13, wherein each pipeline supports multiple write attempts for a given write operation.

17. A memory device as described in claim 13, wherein each pipeline supports a pre-read operation for a given write operation.