GATE DRIVER AND DISPLAY DEVICE USING THE SAME
First Claim
1. A gate driver comprising:
- a plurality of stages to which a shift clock is applied through a clock wiring and which are connected in a cascade connection manner through a carry signal and sequentially generate an output voltage through each output terminal,each of the stages includes;
a first transistor configured to pre-charge a Q node;
a second transistor configured to raise the output voltage depending on a voltage of the Q node;
a third transistor configured to charge a QB node;
a fourth transistor configured to lower the output voltage depending on a voltage of the QB node; and
a first capacitor connected between a gate and one of a source or a drain in at least one of the second transistor and the third transistor,wherein the first capacitor has a capacitance greater than a capacitance between the gate and the other one of the source or the drain of the transistor to which the first capacitor is connected, andwherein the first capacitor includes an upper capacitor disposed on an organic passivation layer overlaying the transistors.
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Accused Products
Abstract
A gate driver and a display device using the same are disclosed. The gate driver includes a first transistor configured to pre-charge a Q node, a second transistor configured to raise the output voltage depending on a voltage of the Q node, a third transistor configured to charge a QB node, a fourth transistor configured to lower the output voltage depending on a voltage of the QB node, and a capacitor connected between a gate and a source in at least one of the second transistor and the third transistor. The capacitor has a capacitance greater than a capacitance between the gate and a drain of the transistor to which the capacitor is connected. The capacitor includes an upper capacitor disposed on an organic passivation layer covering the transistors.
15 Citations
20 Claims
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1. A gate driver comprising:
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a plurality of stages to which a shift clock is applied through a clock wiring and which are connected in a cascade connection manner through a carry signal and sequentially generate an output voltage through each output terminal, each of the stages includes; a first transistor configured to pre-charge a Q node; a second transistor configured to raise the output voltage depending on a voltage of the Q node; a third transistor configured to charge a QB node; a fourth transistor configured to lower the output voltage depending on a voltage of the QB node; and a first capacitor connected between a gate and one of a source or a drain in at least one of the second transistor and the third transistor, wherein the first capacitor has a capacitance greater than a capacitance between the gate and the other one of the source or the drain of the transistor to which the first capacitor is connected, and wherein the first capacitor includes an upper capacitor disposed on an organic passivation layer overlaying the transistors. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A display device comprising:
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a display panel in which data lines and gate lines intersect, pixels are arranged in a matrix form; and a display driver configured to write data of an input image to the pixels, the display driver including a shift register configured to sequentially supply a gate pulse to the gate lines, the shift register including; a plurality of stages to which a shift clock is applied through a clock wiring and which are connected in a cascade connection manner through a carry signal and sequentially generate an output voltage through each output terminal, wherein each of the stages includes; a first transistor configured to pre-charge a Q node; a second transistor configured to raise the output voltage depending on a voltage of the Q node; a third transistor configured to charge a QB node; a fourth transistor configured to lower the output voltage depending on a voltage of the QB node; and a first capacitor connected between a gate and one of a source or a drain in at least one of the second transistor and the third transistor, wherein the first capacitor has a capacitance greater than a capacitance between the gate and another one of the source or the drain of the transistor to which the first capacitor is connected, and wherein the first capacitor includes an upper capacitor disposed on an organic passivation layer overlaying the transistors. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17)
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18. A structure comprising:
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a first metal layer overlying a substrate; an insulation layer overlying the first metal layer; a first aperture in the insulation layer exposing the first metal layer; a second metal layer overlying the insulation layer and the first metal layer to create a lower capacitive element; a first passivation layer overlying the second metal layer, a second aperture in the first passivation layer exposing the second metal layer; a third metal layer overlying the first passivation layer, the first metal layer, the insulation layer and the second metal layer; a second passivation layer overlying the third metal layer; a third aperture in the second passivation layer exposing the third metal layer; a fourth metal layer overlying the third metal layer and the second passivation layer to create an upper capacitive element; a metal connection extending from the first aperture to the third aperture that electrically connects the first metal layer of the lower capacitive element to the third metal layer of the upper capacitive element; and a metal connection extending from the second aperture to the fourth metal layer that electrically connects the second metal layer to the fourth metal layer of the upper capacitive element. - View Dependent Claims (19, 20)
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Specification